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Searched refs:sdhci_writel (Results 1 – 6 of 6) sorted by relevance

/rk3399_rockchip-uboot/drivers/mmc/
H A Dkona_sdhci.c35 sdhci_writel(host, mask, SDHCI_CORECTRL_OFFSET); in init_kona_mmc_core()
52 sdhci_writel(host, mask, SDHCI_CORECTRL_OFFSET); in init_kona_mmc_core()
56 sdhci_writel(host, mask | SDHCI_CORECTRL_EN, SDHCI_CORECTRL_OFFSET); in init_kona_mmc_core()
59 sdhci_writel(host, SDHCI_COREIMR_IP, SDHCI_COREIMR_OFFSET); in init_kona_mmc_core()
63 sdhci_writel(host, mask | SDHCI_CORESTAT_CD_SW, SDHCI_CORESTAT_OFFSET); in init_kona_mmc_core()
H A Dxenon_sdhci.c136 sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST); in xenon_mmc_phy_init()
157 sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST); in xenon_mmc_phy_init()
207 sdhci_writel(host, var, EMMC_PHY_PAD_CONTROL); in xenon_mmc_phy_set()
213 sdhci_writel(host, var, EMMC_PHY_PAD_CONTROL1); in xenon_mmc_phy_set()
228 sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST); in xenon_mmc_phy_set()
246 sdhci_writel(host, var, EMMC_PHY_FUNC_CONTROL); in xenon_mmc_phy_set()
267 sdhci_writel(host, var, SDHC_SYS_OP_CTRL); in xenon_mmc_set_acg()
279 sdhci_writel(host, var, SDHC_SYS_OP_CTRL); in xenon_mmc_enable_slot()
289 sdhci_writel(host, var, SDHC_SYS_EXT_OP_CTRL); in xenon_mmc_enable_parallel_tran()
299 sdhci_writel(host, var, SDHC_SLOT_RETUNING_REQ_CTRL); in xenon_mmc_disable_tuning()
[all …]
H A Drockchip_sdhci.c343 sdhci_writel(host, DWCMSHC_EMMC_DLL_CTRL_RESET, DWCMSHC_EMMC_DLL_CTRL); in dwcmshc_sdhci_emmc_set_clock()
345 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL); in dwcmshc_sdhci_emmc_set_clock()
350 sdhci_writel(host, extra, DWCMSHC_EMMC_ATCTRL); in dwcmshc_sdhci_emmc_set_clock()
356 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL); in dwcmshc_sdhci_emmc_set_clock()
374 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK); in dwcmshc_sdhci_emmc_set_clock()
389 sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT); in dwcmshc_sdhci_emmc_set_clock()
398 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK); in dwcmshc_sdhci_emmc_set_clock()
405 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); in dwcmshc_sdhci_emmc_set_clock()
408 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL); in dwcmshc_sdhci_emmc_set_clock()
413 sdhci_writel(host, extra, DWCMSHC_HOST_CTRL3); in dwcmshc_sdhci_emmc_set_clock()
[all …]
H A Dsdhci.c67 sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER); in sdhci_transfer_pio()
96 sdhci_writel(host, rdy, SDHCI_INT_STATUS); in sdhci_transfer_data()
110 sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS); in sdhci_transfer_data()
113 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); in sdhci_transfer_data()
177 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
188 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
251 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
263 sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
290 sdhci_writel(host, mask, SDHCI_INT_STATUS);
301 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
[all …]
H A Ds5p_sdhci.c40 sdhci_writel(host, SDHCI_CTRL4_DRIVE_MASK(0x3), SDHCI_CONTROL4); in s5p_sdhci_set_control_reg()
50 sdhci_writel(host, val, SDHCI_CONTROL2); in s5p_sdhci_set_control_reg()
62 sdhci_writel(host, val, SDHCI_CONTROL3); in s5p_sdhci_set_control_reg()
73 sdhci_writel(host, ctrl, SDHCI_CONTROL2); in s5p_sdhci_set_control_reg()
/rk3399_rockchip-uboot/include/
H A Dsdhci.h300 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) in sdhci_writel() function
350 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) in sdhci_writel() function