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Searched refs:sdhci_readl (Results 1 – 7 of 7) sorted by relevance

/rk3399_rockchip-uboot/drivers/mmc/
H A Dxenon_sdhci.c128 var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST); in xenon_mmc_phy_init()
142 var = sdhci_readl(host, SDHCI_CLOCK_CONTROL); in xenon_mmc_phy_init()
155 var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST); in xenon_mmc_phy_init()
168 var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST); in xenon_mmc_phy_init()
204 var = sdhci_readl(host, EMMC_PHY_PAD_CONTROL); in xenon_mmc_phy_set()
210 var = sdhci_readl(host, EMMC_PHY_PAD_CONTROL1); in xenon_mmc_phy_set()
226 var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST); in xenon_mmc_phy_set()
235 var = sdhci_readl(host, SDHCI_CLOCK_CONTROL); in xenon_mmc_phy_set()
239 var = sdhci_readl(host, EMMC_PHY_FUNC_CONTROL); in xenon_mmc_phy_set()
249 var = sdhci_readl(host, SDHCI_CLOCK_CONTROL); in xenon_mmc_phy_set()
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H A Dkona_sdhci.c34 mask = sdhci_readl(host, SDHCI_CORECTRL_OFFSET) | SDHCI_CORECTRL_RESET; in init_kona_mmc_core()
47 (sdhci_readl(host, SDHCI_CORECTRL_OFFSET) & in init_kona_mmc_core()
55 mask = sdhci_readl(host, SDHCI_CORECTRL_OFFSET); in init_kona_mmc_core()
62 mask = sdhci_readl(host, SDHCI_CORESTAT_OFFSET); in init_kona_mmc_core()
67 while (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) { in init_kona_mmc_core()
H A Dsdhci.c47 cmd->response[i] = sdhci_readl(host, in sdhci_cmd_done()
54 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE); in sdhci_cmd_done()
65 *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER); in sdhci_transfer_pio()
87 stat = sdhci_readl(host, SDHCI_INT_STATUS); in sdhci_transfer_data()
94 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)) in sdhci_transfer_data()
170 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
273 stat = sdhci_readl(host, SDHCI_INT_STATUS);
300 stat = sdhci_readl(host, SDHCI_INT_STATUS);
346 while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
489 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
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H A Datmel_sdhci.c81 caps = sdhci_readl(host, SDHCI_CAPABILITIES); in atmel_sdhci_probe()
83 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); in atmel_sdhci_probe()
H A Drockchip_sdhci.c212 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & in rockchip_emmc_set_clock()
363 if (DLL_LOCK_WO_TMOUT((sdhci_readl(host, DWCMSHC_EMMC_DLL_STATUS0)))) in dwcmshc_sdhci_emmc_set_clock()
368 dll_lock_value = ((sdhci_readl(host, DWCMSHC_EMMC_DLL_STATUS0) & 0xFF) * 2 ) & 0xFF; in dwcmshc_sdhci_emmc_set_clock()
411 extra = sdhci_readl(host, DWCMSHC_HOST_CTRL3); in dwcmshc_sdhci_emmc_set_clock()
443 vendor = sdhci_readl(host, DWCMSHC_EMMC_CONTROL); in dwcmshc_sdhci_set_enhanced_strobe()
H A Ds5p_sdhci.c42 val = sdhci_readl(host, SDHCI_CONTROL2); in s5p_sdhci_set_control_reg()
70 ctrl = sdhci_readl(host, SDHCI_CONTROL2); in s5p_sdhci_set_control_reg()
/rk3399_rockchip-uboot/include/
H A Dsdhci.h324 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) in sdhci_readl() function
364 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) in sdhci_readl() function