Searched refs:reg_ctrl (Results 1 – 6 of 6) sorted by relevance
| /rk3399_rockchip-uboot/drivers/spi/ |
| H A D | mxc_spi.c | 134 s32 reg_ctrl, reg_config; in spi_cfg_mxc() local
146 reg_ctrl = MXC_CSPICTRL_MODE_MASK; in spi_cfg_mxc()
147 reg_write(®s->ctrl, reg_ctrl); in spi_cfg_mxc()
148 reg_ctrl |= MXC_CSPICTRL_EN; in spi_cfg_mxc()
149 reg_write(®s->ctrl, reg_ctrl); in spi_cfg_mxc()
169 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) | in spi_cfg_mxc()
171 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) | in spi_cfg_mxc()
173 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) | in spi_cfg_mxc()
202 debug("reg_ctrl = 0x%x\n", reg_ctrl); in spi_cfg_mxc()
203 reg_write(®s->ctrl, reg_ctrl); in spi_cfg_mxc()
[all …]
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| /rk3399_rockchip-uboot/drivers/crypto/rockchip/ |
| H A D | crypto_v2.c | 375 u32 reg_ctrl = 0; in rk_hash_init() local
381 reg_ctrl = CRYPTO_SW_CC_RESET; in rk_hash_init()
382 crypto_write(reg_ctrl | (reg_ctrl << CRYPTO_WRITE_MASK_SHIFT), in rk_hash_init()
389 reg_ctrl = 0; in rk_hash_init()
394 reg_ctrl |= CRYPTO_MODE_MD5; in rk_hash_init()
399 reg_ctrl |= CRYPTO_MODE_SHA1; in rk_hash_init()
404 reg_ctrl |= CRYPTO_MODE_SHA256; in rk_hash_init()
409 reg_ctrl |= CRYPTO_MODE_SHA512; in rk_hash_init()
414 reg_ctrl |= CRYPTO_MODE_SM3; in rk_hash_init()
423 reg_ctrl |= CRYPTO_HW_PAD_ENABLE; in rk_hash_init()
[all …]
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-sunxi/ |
| H A D | display.h | 140 u32 reg_ctrl; /* 0x870 */ member
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| /rk3399_rockchip-uboot/arch/arm/mach-imx/mx6/ |
| H A D | ddr.c | 61 static void modify_dg_result(u32 *reg_st0, u32 *reg_st1, u32 *reg_ctrl) in modify_dg_result() argument
70 val_ctrl = readl(reg_ctrl); in modify_dg_result()
85 writel(val_ctrl, reg_ctrl); in modify_dg_result()
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| /rk3399_rockchip-uboot/drivers/net/ |
| H A D | e1000.c | 1507 uint32_t reg_ctrl, reg_ctrl_ext; in e1000_initialize_hardware_bits() local
1557 reg_ctrl = E1000_READ_REG(hw, CTRL); in e1000_initialize_hardware_bits()
1558 reg_ctrl &= ~(1 << 29); in e1000_initialize_hardware_bits()
1561 E1000_WRITE_REG(hw, CTRL, reg_ctrl); in e1000_initialize_hardware_bits()
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| /rk3399_rockchip-uboot/drivers/video/sunxi/ |
| H A D | sunxi_display.c | 514 setbits_le32(&de_be->reg_ctrl, SUNXI_DE_BE_REG_CTRL_LOAD_REGS); in sunxi_composer_enable()
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