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Searched refs:post_div (Results 1 – 9 of 9) sorted by relevance

/rk3399_rockchip-uboot/drivers/clk/aspeed/
H A Dclk_ast2500.c46 unsigned int post_div; member
58 const ulong post_div = (mpll_reg & SCU_MPLL_POST_MASK) in ast2500_get_mpll_rate() local
61 return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1); in ast2500_get_mpll_rate()
73 const ulong post_div = (hpll_reg & SCU_HPLL_POST_MASK) in ast2500_get_hpll_rate() local
76 return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1); in ast2500_get_hpll_rate()
194 for (it.post_div = 0; it.post_div <= max_vals.post_div; in ast2500_calc_clock_config()
195 ++it.post_div) { in ast2500_calc_clock_config()
196 it.num = (rate_khz * (it.post_div + 1) / input_rate_khz) in ast2500_calc_clock_config()
203 / (it.post_div + 1); in ast2500_calc_clock_config()
228 .post_div = (SCU_MPLL_POST_MASK >> SCU_MPLL_POST_SHIFT), in ast2500_configure_ddr()
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/rk3399_rockchip-uboot/drivers/spi/
H A Dmxc_spi.c136 u32 pre_div = 0, post_div = 0; in spi_cfg_mxc() local
154 post_div = fls(pre_div); in spi_cfg_mxc()
155 if (post_div > 4) { in spi_cfg_mxc()
156 post_div -= 4; in spi_cfg_mxc()
157 if (post_div >= 16) { in spi_cfg_mxc()
162 pre_div >>= post_div; in spi_cfg_mxc()
164 post_div = 0; in spi_cfg_mxc()
168 debug("pre_div = %d, post_div=%d\n", pre_div, post_div); in spi_cfg_mxc()
174 MXC_CSPICTRL_POSTDIV(post_div); in spi_cfg_mxc()
/rk3399_rockchip-uboot/arch/arm/mach-davinci/
H A Dcpu.c59 int post_div; in clk_get() local
89 post_div = (readl(pll_base + PLLC_POSTDIV) & in clk_get()
92 pll_out /= post_div; in clk_get()
/rk3399_rockchip-uboot/arch/arm/mach-imx/mx6/
H A Dclock.c553 u32 post_div) in enable_pll_video() argument
569 switch (post_div) { in enable_pll_video()
627 u32 pll_div, pll_num, pll_denom, post_div = 1; in mxs_set_lcdclk() local
664 for (post_div = 2; post_div <= 4; post_div <<= 1) { in mxs_set_lcdclk()
665 if ((temp * post_div) > min) { in mxs_set_lcdclk()
666 freq *= post_div; in mxs_set_lcdclk()
671 if (post_div > 4) { in mxs_set_lcdclk()
711 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div)) in mxs_set_lcdclk()
748 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div)) in mxs_set_lcdclk()
/rk3399_rockchip-uboot/arch/arm/mach-imx/mx7/
H A Dclock.c475 enum root_post_div post_div; in get_ddrc_clk() local
485 post_div = reg & DRAM_CLK_ROOT_POST_DIV_MASK; in get_ddrc_clk()
487 return freq / (post_div + 1) / 2; in get_ddrc_clk()
777 u32 post_div) in enable_pll_video() argument
795 switch (post_div) { in enable_pll_video()
899 u32 pll_div, pll_num, pll_denom, post_div = 0; in mxs_set_lcdclk() local
910 post_div = i; in mxs_set_lcdclk()
947 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div)) in mxs_set_lcdclk()
H A Dclock_slice.c673 enum root_post_div post_div, enum clk_root_src clock_src) in clock_root_cfg() argument
699 if (post_div > CLK_ROOT_POST_DIV7) { in clock_root_cfg()
706 if (post_div != CLK_ROOT_POST_DIV1) { in clock_root_cfg()
717 post_div << CLK_ROOT_POST_DIV_SHIFT | in clock_root_cfg()
/rk3399_rockchip-uboot/board/gdsys/common/
H A Dosd.c81 unsigned int *post_div, unsigned int *feedback_div) in mpc92469ac_calc_parameters() argument
83 unsigned int n = *post_div; in mpc92469ac_calc_parameters()
101 *post_div = n; in mpc92469ac_calc_parameters()
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-mx7/
H A Dclock_slice.h112 enum root_post_div post_div, enum clk_root_src clock_src);
/rk3399_rockchip-uboot/drivers/video/
H A Dati_radeon_fb.h224 int post_div; member