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Searched refs:pll_ctrl (Results 1 – 11 of 11) sorted by relevance

/rk3399_rockchip-uboot/drivers/usb/host/
H A Dehci-vf.c63 void __iomem *pll_ctrl; in usb_power_config() local
67 pll_ctrl = &anadig->pll3_ctrl; in usb_power_config()
68 clrbits_le32(pll_ctrl, ANADIG_PLL3_CTRL_BYPASS); in usb_power_config()
69 setbits_le32(pll_ctrl, ANADIG_PLL3_CTRL_ENABLE in usb_power_config()
74 pll_ctrl = &anadig->pll7_ctrl; in usb_power_config()
75 clrbits_le32(pll_ctrl, ANADIG_PLL7_CTRL_BYPASS); in usb_power_config()
76 setbits_le32(pll_ctrl, ANADIG_PLL7_CTRL_ENABLE in usb_power_config()
/rk3399_rockchip-uboot/drivers/phy/
H A Dphy-rockchip-samsung-hdptx.c927 const struct tx_pll_ctrl *pll_ctrl = &tx_pll_ctrl_extra[bw_extra]; in rockchip_hdptx_phy_set_rate() local
930 FIELD_PREP(ROPLL_PMS_MDIV, pll_ctrl->mdiv)); in rockchip_hdptx_phy_set_rate()
932 FIELD_PREP(ROPLL_SDM_DENOMINATOR, pll_ctrl->sdm_denominator)); in rockchip_hdptx_phy_set_rate()
934 FIELD_PREP(ROPLL_SDM_NUMERATOR, pll_ctrl->sdm_numerator)); in rockchip_hdptx_phy_set_rate()
936 FIELD_PREP(ROPLL_SDC_NUMERATOR, pll_ctrl->sdc_numerator)); in rockchip_hdptx_phy_set_rate()
938 FIELD_PREP(ROPLL_SDC_DENOMINATOR, pll_ctrl->sdc_denominator)); in rockchip_hdptx_phy_set_rate()
942 FIELD_PREP(ROPLL_PMS_SDIV_RBR, pll_ctrl->sdiv)); in rockchip_hdptx_phy_set_rate()
945 pll_ctrl->sdm_numerator_sign)); in rockchip_hdptx_phy_set_rate()
947 FIELD_PREP(ROPLL_SDC_N_RBR, pll_ctrl->sdc_clock_div)); in rockchip_hdptx_phy_set_rate()
950 FIELD_PREP(ROPLL_PMS_SDIV_HBR, pll_ctrl->sdiv)); in rockchip_hdptx_phy_set_rate()
[all …]
/rk3399_rockchip-uboot/arch/m68k/include/asm/
H A Dimmap_5282.h90 typedef struct pll_ctrl { struct
H A Dimmap_520x.h177 typedef struct pll_ctrl { struct
H A Dimmap_5235.h207 typedef struct pll_ctrl { struct
H A Dimmap_5301x.h297 typedef struct pll_ctrl { struct
H A Dimmap_5329.h375 typedef struct pll_ctrl { struct
H A Dimmap_5275.h341 typedef struct pll_ctrl { struct
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-sunxi/
H A Ddisplay.h179 u32 pll_ctrl; /* 0x208 */ member
/rk3399_rockchip-uboot/drivers/video/sunxi/
H A Dsunxi_display.c221 &hdmi->pll_ctrl); in sunxi_hdmi_edid_get_mode()
874 writel(SUNXI_HDMI_PLL_CTRL, &hdmi->pll_ctrl);
878 clrsetbits_le32(&hdmi->pll_ctrl, SUNXI_HDMI_PLL_CTRL_DIV_MASK,
/rk3399_rockchip-uboot/arch/arm/dts/
H A Ddra7.dtsi1330 <0x4A096800 0x40>; /* pll_ctrl */
1331 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1437 reg-names = "phy_rx", "phy_tx", "pll_ctrl";