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Searched refs:m2 (Results 1 – 22 of 22) sorted by relevance

/rk3399_rockchip-uboot/post/lib_powerpc/fpu/
H A D20010226-1.c23 volatile long double m2; in fpu_post_test_math3() local
27 m2 = m1 * 4294967296.0; in fpu_post_test_math3()
28 mant_long = ((unsigned long) m2) & 0xffffffff; in fpu_post_test_math3()
/rk3399_rockchip-uboot/arch/arm/mach-omap2/omap3/
H A Dclock.c154 0xF8000000, ptr->m2 << 27); in dpll3_init_34xx()
208 clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27); in dpll3_init_34xx()
266 clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, (ptr->m2 + 1)); in dpll4_init_34xx()
267 clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2); in dpll4_init_34xx()
297 clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2); in dpll5_init_34xx()
321 0x0000001F, ptr->m2); in mpu_init_34xx()
352 0x0000001F, ptr->m2); in iva_init_34xx()
404 0xF8000000, ptr->m2 << 27); in dpll3_init_36xx()
458 clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27); in dpll3_init_36xx()
509 clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2); in dpll4_init_36xx()
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/rk3399_rockchip-uboot/arch/arm/include/asm/arch-omap3/
H A Dclock.h36 unsigned int m2; member
43 unsigned int m2; member
/rk3399_rockchip-uboot/scripts/dtc/
H A Ddata.c157 struct marker *m2 = d2.markers; in data_merge() local
159 d = data_append_markers(data_append_data(d1, d2.val, d2.len), m2); in data_merge()
162 for_each_marker(m2) in data_merge()
163 m2->offset += d1.len; in data_merge()
/rk3399_rockchip-uboot/arch/arm/dts/
H A Dsun6i-a31s-sinovoip-bpi-m2.dts50 compatible = "sinovoip,bpi-m2", "allwinner,sun6i-a31s";
66 label = "bpi-m2:blue:usr";
71 label = "bpi-m2:green:usr";
76 label = "bpi-m2:red:usr";
H A Dsun8i-h3-bananapi-m2-plus.dts53 compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3";
70 label = "bananapi-m2-plus:red:pwr";
H A Dsun8i-r40-bananapi-m2-ultra.dts48 compatible = "sinovoip,bpi-m2-ultra", "allwinner,sun8i-r40";
H A DMakefile273 sun6i-a31s-sinovoip-bpi-m2.dtb \
324 sun8i-h3-bananapi-m2-plus.dtb \
337 sun8i-r40-bananapi-m2-ultra.dtb
/rk3399_rockchip-uboot/configs/
H A DBananapi_M2_Ultra_defconfig9 CONFIG_DEFAULT_DEVICE_TREE="sun8i-r40-bananapi-m2-ultra"
H A DSinovoip_BPI_M2_Plus_defconfig9 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-bananapi-m2-plus"
H A DSinovoip_BPI_M2_defconfig7 CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-sinovoip-bpi-m2"
/rk3399_rockchip-uboot/arch/xtensa/include/asm/arch-de212/
H A Dtie.h75 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/
H A Dfit_args.sh70 -m2)
/rk3399_rockchip-uboot/arch/xtensa/include/asm/arch-dc232b/
H A Dtie.h97 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
/rk3399_rockchip-uboot/arch/xtensa/include/asm/arch-dc233c/
H A Dtie.h98 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
/rk3399_rockchip-uboot/arch/arm/mach-omap2/am33xx/
H A Dclock.c22 if (params->m2 >= 0) in setup_post_dividers()
23 writel(params->m2, dpll_regs->cm_div_m2_dpll); in setup_post_dividers()
H A Dclock_ti814x.c224 static void pll_config(u32 base, u32 n, u32 m, u32 m2, in pll_config() argument
231 m2nval = (m2 << ADPLLJ_M2NDIV_M2SHIFT) | n; in pll_config()
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-am33xx/
H A Dclock.h84 s8 m2; member
/rk3399_rockchip-uboot/arch/arm/mach-omap2/
H A Dclocks-common.c79 if (params->m2 >= 0) in setup_post_dividers()
80 writel(params->m2, &dpll_regs->cm_div_m2_dpll); in setup_post_dividers()
298 ddr_clk = ddr_clk / divider / core_dpll_params->m2; in omap_ddr_clk()
753 freq_config1 |= (core_dpll_params->m2 << in freq_update_core()
/rk3399_rockchip-uboot/tools/rockchip/
H A Dsha2.c554 static sha2_64t m2[8] = { n_u64(0000000000000000), n_u64(ff00000000000000), variable
579 ctx->wbuf[i >> 3] = (ctx->wbuf[i >> 3] & m2[i & 7]) | b2[i & 7]; in sha_end()
/rk3399_rockchip-uboot/board/sunxi/
H A DMAINTAINERS128 F: arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts
/rk3399_rockchip-uboot/arch/arm/include/asm/
H A Domap_common.h491 s8 m2; member