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Searched refs:link_cfg (Results 1 – 8 of 8) sorted by relevance

/rk3399_rockchip-uboot/drivers/video/tegra124/
H A Ddp.c416 const struct tegra_dp_link_config *link_cfg) in tegra_dc_dp_dump_link_cfg() argument
420 link_cfg->max_lane_count); in tegra_dc_dp_dump_link_cfg()
422 link_cfg->support_enhanced_framing ? "Y" : "N"); in tegra_dc_dp_dump_link_cfg()
424 link_cfg->max_link_bw); in tegra_dc_dp_dump_link_cfg()
426 link_cfg->bits_per_pixel); in tegra_dc_dp_dump_link_cfg()
428 link_cfg->enhanced_framing ? "Y" : "N"); in tegra_dc_dp_dump_link_cfg()
430 link_cfg->scramble_ena ? "Y" : "N"); in tegra_dc_dp_dump_link_cfg()
432 link_cfg->link_bw); in tegra_dc_dp_dump_link_cfg()
434 link_cfg->lane_count); in tegra_dc_dp_dump_link_cfg()
436 link_cfg->activepolarity); in tegra_dc_dp_dump_link_cfg()
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H A Dsor.c144 const struct tegra_dp_link_config *link_cfg) in tegra_dc_sor_set_dp_linkctl() argument
157 reg_val |= (link_cfg->tu_size << DP_LINKCTL_TUSIZE_SHIFT); in tegra_dc_sor_set_dp_linkctl()
159 if (link_cfg->enhanced_framing) in tegra_dc_sor_set_dp_linkctl()
170 reg_val = (link_cfg->link_bw == SOR_LINK_SPEED_G5_4) ? in tegra_dc_sor_set_dp_linkctl()
277 const struct tegra_dp_link_config *link_cfg) in tegra_dc_sor_set_dp_mode() argument
282 tegra_dc_sor_set_link_bandwidth(dev, link_cfg->link_bw); in tegra_dc_sor_set_dp_mode()
284 tegra_dc_sor_set_dp_linkctl(dev, 1, training_pattern_none, link_cfg); in tegra_dc_sor_set_dp_mode()
287 reg_val |= link_cfg->watermark; in tegra_dc_sor_set_dp_mode()
289 reg_val |= (link_cfg->active_count << in tegra_dc_sor_set_dp_mode()
292 reg_val |= (link_cfg->active_frac << in tegra_dc_sor_set_dp_mode()
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H A Dsor.h880 const struct tegra_dp_link_config *link_cfg);
883 u8 training_pattern, const struct tegra_dp_link_config *link_cfg);
892 const struct tegra_dp_link_config *link_cfg);
894 const struct tegra_dp_link_config *link_cfg);
896 const struct tegra_dp_link_config *link_cfg);
904 const struct tegra_dp_link_config *link_cfg,
/rk3399_rockchip-uboot/drivers/i2c/muxes/
H A Dmax96755f.c18 int link_cfg; in max96755f_select() local
26 link_cfg = dm_i2c_reg_read(priv->dev, 0x0010); in max96755f_select()
27 if ((link_cfg & LINK_CFG) == SPLITTER_MODE) in max96755f_select()
30 if (channel == 0 && (link_cfg & LINK_CFG) != LINKA) { in max96755f_select()
37 } else if (channel == 1 && (link_cfg & LINK_CFG) != LINKB) { in max96755f_select()
/rk3399_rockchip-uboot/drivers/video/drm/
H A Drockchip_dw_hdmi_qp.c173 struct dw_hdmi_link_config link_cfg; member
531 u64 frl_rate = (u64)hdmi->link_cfg.frl_lanes * in rockchip_hdmi_if_dsc_enable()
532 hdmi->link_cfg.rate_per_lane * 1000000; in rockchip_hdmi_if_dsc_enable()
561 hdmi->link_cfg.dsc_mode = false; in hdmi_select_link_config()
562 hdmi->link_cfg.frl_lanes = max_lanes; in hdmi_select_link_config()
563 hdmi->link_cfg.rate_per_lane = max_rate_per_lane; in hdmi_select_link_config()
564 hdmi->link_cfg.allm_en = hdmi->allm_en; in hdmi_select_link_config()
569 hdmi->link_cfg.frl_mode = false; in hdmi_select_link_config()
573 hdmi->link_cfg.frl_mode = true; in hdmi_select_link_config()
583 hdmi->link_cfg.dsc_mode = true; in hdmi_select_link_config()
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H A Ddw_hdmi_qp.c757 struct dw_hdmi_link_config *link_cfg = NULL; in hdmi_config_vendor_specific_infoframe() local
763 link_cfg = dw_hdmi_rockchip_get_link_cfg(hdmi->rk_hdmi); in hdmi_config_vendor_specific_infoframe()
770 if (link_cfg->allm_en) { in hdmi_config_vendor_specific_infoframe()
831 struct dw_hdmi_link_config *link_cfg) in hdmi_config_CVTEM() argument
848 if (!link_cfg->dsc_mode) { in hdmi_config_CVTEM()
853 pps_body = link_cfg->pps_payload; in hdmi_config_CVTEM()
903 val = link_cfg->hcactive << 8 | ((hback >> 8) & 0xff); in hdmi_config_CVTEM()
1023 struct dw_hdmi_link_config *link_cfg, in hdmi_set_op_mode() argument
1030 if (!link_cfg->frl_mode) { in hdmi_set_op_mode()
1039 if (link_cfg->frl_lanes == 4) in hdmi_set_op_mode()
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/rk3399_rockchip-uboot/drivers/video/drm/display-serdes/maxim/
H A Dmaxim-max96755.c648 u32 link_cfg; in max96755_select() local
654 serdes_reg_read(serdes, 0x0010, &link_cfg); in max96755_select()
655 if ((link_cfg & LINK_CFG) == SPLITTER_MODE) in max96755_select()
658 serdes->chip_data->name, link_cfg); in max96755_select()
660 if (chan == 0 && (link_cfg & LINK_CFG) != DUAL_LINK) { in max96755_select()
671 } else if (chan == 1 && (link_cfg & LINK_CFG) != LINKA) { in max96755_select()
682 } else if (chan == 2 && (link_cfg & LINK_CFG) != LINKB) { in max96755_select()
693 } else if (chan == 3 && (link_cfg & LINK_CFG) != SPLITTER_MODE) { in max96755_select()
H A Dmaxim-max96789.c650 u32 link_cfg, link_status; in max96789_select() local
658 serdes_reg_read(serdes, 0x0010, &link_cfg); in max96789_select()
659 if ((link_cfg & LINK_CFG) == SPLITTER_MODE) in max96789_select()
662 serdes->chip_data->name, link_cfg); in max96789_select()
664 if (chan == 0 && (link_cfg & LINK_CFG) != DUAL_LINK) { in max96789_select()
676 } else if (chan == 1 && (link_cfg & LINK_CFG) != LINKA) { in max96789_select()
688 } else if (chan == 2 && (link_cfg & LINK_CFG) != LINKB) { in max96789_select()
700 } else if (chan == 3 && (link_cfg & LINK_CFG) != SPLITTER_MODE) { in max96789_select()