| /rk3399_rockchip-uboot/drivers/sound/ |
| H A D | sound.c | 16 const int half = period / 2; in sound_create_square_wave() local
26 for (i = 0; size && i < half; i++) { in sound_create_square_wave()
31 for (i = 0; size && i < period - half; i++) { in sound_create_square_wave()
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| /rk3399_rockchip-uboot/doc/ |
| H A D | README.t1040-l2switch | 53 0 enabled down 10 half
54 1 enabled down 10 half
55 2 enabled down 10 half
57 4 disabled down - half
58 5 disabled down - half
59 6 disabled down - half
60 7 disabled down - half
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| /rk3399_rockchip-uboot/doc/device-tree-bindings/net/ |
| H A D | fixed-link.txt | 15 used. When absent, half duplex is assumed.
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| /rk3399_rockchip-uboot/drivers/mtd/spi/ |
| H A D | spi-nor-core.c | 1769 u16 half, in spi_nor_set_read_settings_from_bfpt() argument
1772 read->num_mode_clocks = (half >> 5) & 0x07; in spi_nor_set_read_settings_from_bfpt()
1773 read->num_wait_states = (half >> 0) & 0x1f; in spi_nor_set_read_settings_from_bfpt()
1774 read->opcode = (half >> 8) & 0xff; in spi_nor_set_read_settings_from_bfpt()
1955 u16 half; in spi_nor_parse_bfpt() local
2020 half = bfpt.dwords[rd->settings_dword] >> rd->settings_shift; in spi_nor_parse_bfpt()
2021 spi_nor_set_read_settings_from_bfpt(read, half, rd->proto); in spi_nor_parse_bfpt()
2030 half = bfpt.dwords[er->dword] >> er->shift; in spi_nor_parse_bfpt()
2031 erasesize = half & 0xff; in spi_nor_parse_bfpt()
2038 opcode = (half >> 8) & 0xff; in spi_nor_parse_bfpt()
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| /rk3399_rockchip-uboot/board/freescale/mpc8641hpcn/ |
| H A D | README | 83 It is possible to use either half to boot using U-Boot. Switch 5 bit 2
91 Use the above mentioned flash commands to program the other half, and
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| /rk3399_rockchip-uboot/doc/driver-model/ |
| H A D | i2c-howto.txt | 4 Over half of the I2C drivers have been converted as at November 2016. These
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| /rk3399_rockchip-uboot/board/Seagate/nas220/ |
| H A D | kwbimage.cfg | 116 # bit9 : 0 , no half clock cycle addition to dataout
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| /rk3399_rockchip-uboot/doc/device-tree-bindings/spi/ |
| H A D | spi-bus.txt | 62 - spi-half-duplex - (optional) Indicates that the SPI bus should wait for
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| /rk3399_rockchip-uboot/board/Marvell/guruplug/ |
| H A D | kwbimage.cfg | 112 # bit9 : 0 , no half clock cycle addition to dataout
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| /rk3399_rockchip-uboot/board/Seagate/dockstar/ |
| H A D | kwbimage.cfg | 115 # bit9 : 0 , no half clock cycle addition to dataout
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| /rk3399_rockchip-uboot/board/Synology/ds109/ |
| H A D | kwbimage.cfg | 116 # bit9 : 0 , no half clock cycle addition to dataout
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| /rk3399_rockchip-uboot/board/Marvell/dreamplug/ |
| H A D | kwbimage.cfg | 113 # bit9 : 0 , no half clock cycle addition to dataout
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| /rk3399_rockchip-uboot/board/Seagate/goflexhome/ |
| H A D | kwbimage.cfg | 118 # bit9 : 0 , no half clock cycle addition to dataout
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| /rk3399_rockchip-uboot/arch/arm/dts/ |
| H A D | exynos5800-peach-pi.dts | 188 spi-half-duplex;
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| /rk3399_rockchip-uboot/board/Marvell/sheevaplug/ |
| H A D | kwbimage.cfg | 112 # bit9 : 0 , no half clock cycle addition to dataout
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| /rk3399_rockchip-uboot/board/LaCie/netspace_v2/ |
| H A D | kwbimage.cfg | 112 # bit9 : 0 , no half clock cycle addition to dataout
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| H A D | kwbimage-is2.cfg | 112 # bit9 : 0 , no half clock cycle addition to dataout
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| H A D | kwbimage-ns2l.cfg | 112 # bit9 : 0 , no half clock cycle addition to dataout
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| /rk3399_rockchip-uboot/board/cloudengines/pogo_e02/ |
| H A D | kwbimage.cfg | 116 # bit9 : 0 , no half clock cycle addition to dataout
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| /rk3399_rockchip-uboot/board/raidsonic/ib62x0/ |
| H A D | kwbimage.cfg | 113 # bit9: 0x0, no half clock cycle addition to dataout
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| /rk3399_rockchip-uboot/board/keymile/km_arm/ |
| H A D | kwbimage.cfg | 124 # bit9 : 0 , no half clock cycle addition to dataout
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| /rk3399_rockchip-uboot/board/LaCie/net2big_v2/ |
| H A D | kwbimage.cfg | 112 # bit9 : 0 , no half clock cycle addition to dataout
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| /rk3399_rockchip-uboot/board/Marvell/openrd/ |
| H A D | kwbimage.cfg | 112 # bit9 : 0 , no half clock cycle addition to dataout
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| /rk3399_rockchip-uboot/board/iomega/iconnect/ |
| H A D | kwbimage.cfg | 112 # bit9: 0x0, no half clock cycle addition to dataout
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| /rk3399_rockchip-uboot/board/freescale/bsc9131rdb/ |
| H A D | README | 35 . ADI lanes support both full duplex FDD support and half duplex TDD support
|