| /rk3399_rockchip-uboot/lib/zlib/ |
| H A D | inffast.c | 96 unsigned char FAR *from; /* where to copy match from */ in inflate_fast() local
203 from = window - OFF; in inflate_fast()
205 from += wsize - op; in inflate_fast()
209 PUP(out) = PUP(from); in inflate_fast()
211 from = out - dist; /* rest from output */ in inflate_fast()
215 from += wsize + write - op; in inflate_fast()
220 PUP(out) = PUP(from); in inflate_fast()
222 from = window - OFF; in inflate_fast()
227 PUP(out) = PUP(from); in inflate_fast()
229 from = out - dist; /* rest from output */ in inflate_fast()
[all …]
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| /rk3399_rockchip-uboot/board/toradex/apalis_imx6/ |
| H A D | pf0100_otp.inc | 13 // Generated from Spreadsheet Revision: P1.8
15 /* sed commands to get from programmer script to struct */
29 {pmic_i2c, 0xA0, 0x2B}, // Auto gen from Row94
30 {pmic_i2c, 0xA1, 0x01}, // Auto gen from Row95
31 {pmic_i2c, 0xA2, 0x05}, // Auto gen from Row96
32 {pmic_i2c, 0xA8, 0x2B}, // Auto gen from Row102
33 {pmic_i2c, 0xA9, 0x02}, // Auto gen from Row103
34 {pmic_i2c, 0xAA, 0x01}, // Auto gen from Row104
35 {pmic_i2c, 0xAC, 0x18}, // Auto gen from Row106
36 {pmic_i2c, 0xAE, 0x01}, // Auto gen from Row108
[all …]
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| /rk3399_rockchip-uboot/board/toradex/colibri_imx6/ |
| H A D | pf0100_otp.inc | 13 // Generated from Spreadsheet Revision: P1.8
15 /* sed commands to get from programmer script to struct */
29 {pmic_i2c, 0xA0, 0x2B}, // Auto gen from Row94
30 {pmic_i2c, 0xA1, 0x01}, // Auto gen from Row95
31 {pmic_i2c, 0xA2, 0x05}, // Auto gen from Row96
32 {pmic_i2c, 0xA8, 0x2B}, // Auto gen from Row102
33 {pmic_i2c, 0xA9, 0x02}, // Auto gen from Row103
34 {pmic_i2c, 0xAA, 0x01}, // Auto gen from Row104
35 {pmic_i2c, 0xAC, 0x18}, // Auto gen from Row106
36 {pmic_i2c, 0xAE, 0x01}, // Auto gen from Row108
[all …]
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| /rk3399_rockchip-uboot/board/phytec/pcm058/ |
| H A D | README | 23 The SOM can boot from NAND or from SD-Card, having the SPI-NOR
28 DIP-1 set to off: Boot first from NAND, then try SPI
29 DIP-1 set to on: Boot first from SD, then try SPI
32 is present, then the RBL tries to load SPL from the SD Card, if not,
33 RBL loads from SPI-NOR. The SPL tries then to load from the same
34 device where SPL was loaded (SD or SPI). Booting from NAND is
|
| /rk3399_rockchip-uboot/lib/lzma/ |
| H A D | README.txt | 2 The original source cames from the LZMA SDK web page:
9 * untars the lzmaXYY.tar.bz2 file (from the download web page)
11 and lzma.txt from source archive into the lib_lzma directory (pwd).
17 Notice: The files from lzma sdk are _not modified_ by this script!
20 function that wraps the complex LzmaDecode() function from the LZMA SDK. The
25 library directly from U-BOOT code without touching the original LZMA SDK's
|
| /rk3399_rockchip-uboot/board/boundary/nitrogen6x/ |
| H A D | README.mx6qsabrelite | 6 1. Boot source, boot from SD card
10 boot from SD card only. However, by default, the SabreLite
11 boards boot from the SPI NOR flash. These boards need to be reflashed with
12 a small SD card loader to support boot from SD card. This small SD card loader
13 will be flashed into the SPI NOR. The board will still boot from SPI NOR, but
14 the loader will in turn request the BootROM to load the U-Boot from SD card.
16 The SD card loader is available from
35 from the fuses.
38 (the default one the board is shipped with, starting from the SPI NOR) and
52 Note: The board now boots from full size SD3 on the bottom of the board. NOT
[all …]
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| /rk3399_rockchip-uboot/board/freescale/mpc8536ds/ |
| H A D | README | 7 Boot from NAND:
10 The MPC8536E is capable of booting from NAND flash which uses the image
20 The 4K NAND loader's code comes from the corresponding nand_spl directory,
25 second stage image. It's set in the board config file when boot from NAND
45 Boot from On-chip ROM:
48 The MPC8536E is capable of booting from the on-chip ROM - boot from eSDHC
49 and boot from eSPI. When power on, the porcessor excutes the ROM code to
50 initialize the eSPI/eSDHC controller, and loads the mian U-Boot image from
52 SPI EEPROM, to the target memory, e.g. SDRAM or L2SRAM, then boot from it.
64 For boot from eSDHC:
[all …]
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| /rk3399_rockchip-uboot/board/phytec/pfla02/ |
| H A D | README | 19 The SOM can boot from NAND or from SD-Card, having the SPI-NOR
23 SW3_1(on), SW3_2(on), SW3_3(off): Boot first from SD, then try SPI
24 SW3_1(off), SW3_2(on), SW3_3(off): Boot from SPI
|
| /rk3399_rockchip-uboot/tools/scripts/ |
| H A D | define2mk.sed | 23 # but remove again from decimal numbers
25 # ... and from negative decimal numbers
27 # ... and from hex numbers
29 # ... and from configs defined from other configs
|
| /rk3399_rockchip-uboot/drivers/mtd/onenand/ |
| H A D | onenand_bbt.c | 69 loff_t from; in create_bbt() local
88 from = 0; in create_bbt()
102 from + j * mtd->writesize + in create_bbt()
114 (unsigned int)from); in create_bbt()
121 rgn = flexonenand_region(mtd, from); in create_bbt()
122 from += mtd->eraseregions[rgn].erasesize; in create_bbt()
124 from += (1 << bbm->bbt_erase_shift); in create_bbt()
|
| /rk3399_rockchip-uboot/common/ |
| H A D | kgdb_stubs.c | 48 void kgdb_flush_cache_range(void *from, void *to) in kgdb_flush_cache_range() argument
50 flush_cache((unsigned long)from, (unsigned long)(to - from)); in kgdb_flush_cache_range()
|
| /rk3399_rockchip-uboot/board/freescale/mx28evk/ |
| H A D | README | 17 To boot MX28EVK from an SD card, set the boot mode DIP switches as:
19 * Boot Mode Select: 1 0 0 1 (Boot from SD card Slot 0 - U42)
26 To boot MX28EVK from SPI NOR flash, set the boot mode DIP switches as:
28 * Boot Mode Select: 0 0 1 0 (Boot from SSP2)
52 Note: The mx28evk board does not come with a NAND flash populated from the
56 mx28evk does not come with SPI NOR flash populated from the factory either.
61 Follow the instructions from doc/README.mxs to generate a bootable SD card or
|
| /rk3399_rockchip-uboot/doc/ |
| H A D | README.arm-relocation | 35 Board.c code is adapted from ppc code
43 For boards which boot from spl, it is possible to save one copy
47 example for the tx25 board booting from NAND Flash:
71 - maybe adapt CONFIG_SYS_TEXT_BASE (this must be checked from board maintainers)
72 This *must* be done for boards, which boot from NOR flash
75 one copying from u-boot code.
82 Relocation with SPL (example for the tx25 booting from NAND Flash):
84 - cpu copies the first page from NAND to 0xbb000000 (IMX_NFC_BASE)
87 - The First page contains u-boot code from drivers/mtd/nand/raw/mxc_nand_spl.c
95 CONFIG_SPL_TEXT_BASE from the spl code), then there is no need
[all …]
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| H A D | README.nand-boot-ppc440 | 8 The PPC440EP(x)/GR(x) cpu's can boot directly from NAND FLASH,
16 Will load first 4k from NAND (SPL) into cache and execute it from there.
20 Will load special U-Boot version (NUB) from NAND and execute it. This SPL
23 loaded from NAND to SDRAM.
29 from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
32 is set up. While still running from cache, I experienced problems accessing
|
| H A D | README.srio-pcie-boot-corenet | 6 configured to SRIO or PCIE by RCW. The processor booting from SRIO or PCIE can
8 from another processor's memory space by SRIO or PCIE link connected between
12 platforms and a RCW example with boot from SRIO or PCIE configuration.
33 Two P4080DS platforms can be used to implement the boot from SRIO or PCIE.
35 the boot from SRIO or PCIE.
37 1. Slave's RCW example for boot from SRIO port 1 and all cores in holdoff.
44 2. Slave's RCW example for boot from PCIE port 1 and all cores in holdoff.
52 a) Update RCW for slave with boot from SRIO or PCIE port 1 configuration.
61 d) Restart up master and it will boot up normally from its NorFlash.
62 Then, it will finish necessary configurations for slave's boot from
[all …]
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| H A D | README.sha1 | 12 -p calculate the SHA1 sum from the U-Boot image in flash and print
16 calculates and prints the SHA1 sum, from the Image stored in Flash
19 check, if the SHA1 sum from the Image stored in Flash is correct
22 It is possible to calculate a SHA1 checksum from a memoryrange with:
30 (for this example we use the Image from Flash, stored at 0xfffa0000 and
47 c) now calculate the SHA1 sum from the memoryrange and write
|
| H A D | README.pblimage | 5 The CoreNet SoC's can boot directly from eSPI FLASH, SD/MMC and
34 1). Boot from eSPI flash
35 Write u-boot.pbl to eSPI flash from offset 0x0.
43 2). Boot from SD/MMC
44 Write u-boot.pbl to SD/MMC from offset 0x1000.
51 3). Boot from Nand
52 Write u-boot.pbl to Nand from offset 0x0.
|
| H A D | README.nokia_rx51 | 4 from NOLO in qemu or on a real N900. It does very little hardware config
14 uImage or boot.scr from a fat, ext2/ext3 or ext4 filesystem in external
23 but is disabled because it prevents the current Maemo kernel from booting.
31 * 1. try boot from external SD card
32 * 2. try boot from internal eMMC memory
33 * 3. try boot from attached kernel image
35 Boot from SD or eMMC in this order:
51 * run sdboot - Boot from external SD card (see boot order)
52 * run emmcboot - Boot from internal eMMC memory (see boot order)
67 Additional variables for loading files from mmc:
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| /rk3399_rockchip-uboot/doc/SPI/ |
| H A D | README.ti_qspi_flash | 11 from Quad SPI flash devices.
16 MLO/u-boot.img will be flashed from SD/MMC to the flash device
19 from the predefined location in the flash, where it was flashed and
21 u-boot.img from flash and execute it from SDRAM.
41 is responsible for transferring the datas from host controller
|
| /rk3399_rockchip-uboot/doc/uImage.FIT/ |
| H A D | command_syntax_extensions.txt | 56 with the ramdisk from the image.
71 from the image at <addr2>.
76 booted with initrd loaded with ramdisk from the image at <addr2>.
88 Ad. 9. Similar to case 2: boot kernel stored in <subimg1> from the image at
92 Ad. 10. Boot configuration <conf> from the image at <addr1>.
96 Ad. 11. Equivalent to case 5: boot kernel stored in <subimg1> from the image
97 at <addr1> with initrd loaded with ramdisk <subimg2> from the image at
101 Ad. 12. Equivalent to case 6: boot kernel stored in <subimg1> from the image
102 at <addr1> with initrd loaded with ramdisk <subimg2> from the image at
103 <addr2>, and pass FDT blob <subimg3> from the image at <addr3>.
[all …]
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| /rk3399_rockchip-uboot/fs/ubifs/ |
| H A D | key.h | 411 static inline void key_read(const struct ubifs_info *c, const void *from, in key_read() argument
414 const union ubifs_key *f = from; in key_read()
427 const union ubifs_key *from, void *to) in key_write() argument
431 t->j32[0] = cpu_to_le32(from->u32[0]); in key_write()
432 t->j32[1] = cpu_to_le32(from->u32[1]); in key_write()
443 const union ubifs_key *from, void *to) in key_write_idx() argument
447 t->j32[0] = cpu_to_le32(from->u32[0]); in key_write_idx()
448 t->j32[1] = cpu_to_le32(from->u32[1]); in key_write_idx()
458 const union ubifs_key *from, union ubifs_key *to) in key_copy() argument
460 to->u64[0] = from->u64[0]; in key_copy()
|
| /rk3399_rockchip-uboot/include/ |
| H A D | onenand_uboot.h | 33 extern int onenand_read(struct mtd_info *mtd, loff_t from, size_t len,
35 extern int onenand_read_oob(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops);
36 extern int onenand_write(struct mtd_info *mtd, loff_t from, size_t len,
|
| /rk3399_rockchip-uboot/arch/arm/include/asm/mach-imx/ |
| H A D | imximage.cfg | 10 * tools/imximage.c can not cross-include headers from arch/arm/
19 /* Specific image header offset for booting from OneNAND. */
21 /* Specific image header offset for booting from memory-mapped NOR. */
|
| /rk3399_rockchip-uboot/board/buffalo/lsxl/ |
| H A D | kwbimage-lschl.cfg | 22 # not further specified in HW manual, timing taken from original vendor port
26 # not further specified in HW manual, timing taken from original vendor port
141 # bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
142 # bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal
143 # bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
144 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
149 # bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
150 # bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
151 # bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
152 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
[all …]
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| H A D | kwbimage-lsxhl.cfg | 22 # not further specified in HW manual, timing taken from original vendor port
26 # not further specified in HW manual, timing taken from original vendor port
141 # bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
142 # bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal
143 # bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
144 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
149 # bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
150 # bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
151 # bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
152 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
[all …]
|