Lines Matching refs:from

22 # not further specified in HW manual, timing taken from original vendor port
26 # not further specified in HW manual, timing taken from original vendor port
141 # bit7-4:   2, 2 cycles from read command to assertion of M_ODT signal
142 # bit11-8:  5, 5 cycles from read command to de-assertion of M_ODT signal
143 # bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
144 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
149 # bit3-0:   2, 2 cycles from write comand to assertion of M_ODT signal
150 # bit7-4:   5, 5 cycles from write command to de-assertion of M_ODT signal
151 # bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
152 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
181 # bit3-0:   0b0000, (read) M_ODT[0] is not asserted during read from DRAM
182 # bit7-4:   0b0000, (read) M_ODT[1] is not asserted during read from DRAM
196 # bit3-0:   0b1111, internal ODT is asserted during read from DRAM bank 0-3