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Searched refs:fpga (Results 1 – 25 of 41) sorted by relevance

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/rk3399_rockchip-uboot/board/gdsys/common/
H A Dcmd_ioloop.c56 static void io_check_status(unsigned int fpga, u16 status, bool silent) in io_check_status() argument
63 FPGA_SET_REG(fpga, ep.rx_tx_status, status); in io_check_status()
68 FPGA_SET_REG(fpga, ep.rx_tx_status, status); in io_check_status()
89 static void io_send(unsigned int fpga, unsigned int size) in io_send() argument
100 FPGA_SET_REG(fpga, ep.transmit_data, *p++); in io_send()
103 FPGA_SET_REG(fpga, ep.transmit_data, k); in io_send()
105 FPGA_SET_REG(fpga, ep.rx_tx_control, in io_send()
111 static void io_receive(unsigned int fpga) in io_receive() argument
116 FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status); in io_receive()
124 FPGA_GET_REG(fpga, ep.receive_data, &rx); in io_receive()
[all …]
H A Dihs_mdio.c22 FPGA_GET_REG(info->fpga, mdio.control, &val); in ihs_mdio_idle()
46 FPGA_SET_REG(info->fpga, mdio.control, in ihs_mdio_read()
52 FPGA_GET_REG(info->fpga, mdio.rx_data, &val); in ihs_mdio_read()
64 FPGA_SET_REG(info->fpga, mdio.address_data, value); in ihs_mdio_write()
65 FPGA_SET_REG(info->fpga, mdio.control, in ihs_mdio_write()
H A Dioep-fpga.c55 bool ioep_fpga_has_osd(unsigned int fpga) in ioep_fpga_has_osd() argument
66 void ioep_fpga_print_info(unsigned int fpga) in ioep_fpga_print_info() argument
82 FPGA_GET_REG(fpga, versions, &versions); in ioep_fpga_print_info()
83 FPGA_GET_REG(fpga, fpga_version, &fpga_version); in ioep_fpga_print_info()
84 FPGA_GET_REG(fpga, fpga_features, &fpga_features); in ioep_fpga_print_info()
H A Dioep-fpga.h11 void ioep_fpga_print_info(unsigned int fpga);
12 bool ioep_fpga_has_osd(unsigned int fpga);
H A DMakefile8 obj-$(CONFIG_SYS_FPGA_COMMON) += fpga.o
15 obj-$(CONFIG_HRCON) += osd.o mclink.o dp501.o phy.o ioep-fpga.o fanctrl.o
16 obj-$(CONFIG_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7301.o
H A Dfpga.c13 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data) in fpga_set_reg() argument
20 int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data) in fpga_get_reg() argument
H A Dihs_mdio.h12 u32 fpga; member
/rk3399_rockchip-uboot/board/xilinx/zynq/
H A Dboard.c19 static xilinx_desc fpga; variable
44 fpga = fpga007s; in board_init()
47 fpga = fpga010; in board_init()
50 fpga = fpga012s; in board_init()
53 fpga = fpga014s; in board_init()
56 fpga = fpga015; in board_init()
59 fpga = fpga020; in board_init()
62 fpga = fpga030; in board_init()
65 fpga = fpga035; in board_init()
68 fpga = fpga045; in board_init()
[all …]
/rk3399_rockchip-uboot/drivers/fpga/
H A Daltera.c100 const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__); in altera_load() local
102 if (!fpga) in altera_load()
106 __func__, fpga->name); in altera_load()
107 if (fpga->load) in altera_load()
108 return fpga->load(desc, buf, bsize); in altera_load()
114 const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__); in altera_dump() local
116 if (!fpga) in altera_dump()
120 __func__, fpga->name); in altera_dump()
121 if (fpga->dump) in altera_dump()
122 return fpga->dump(desc, buf, bsize); in altera_dump()
[all …]
H A DKconfig14 (in BIT format), fpga and device validation.
39 (in BIT format), fpga and device validation.
H A DMakefile8 obj-y += fpga.o
/rk3399_rockchip-uboot/board/gdsys/a38x/
H A Dhydra.c18 static struct ihs_fpga *fpga; variable
22 return fpga; in get_fpga()
27 u32 versions = readl(&fpga->versions); in print_hydra_version()
28 u32 fpga_version = readl(&fpga->fpga_version); in print_hydra_version()
32 printf("FPGA%u: mapped to %p\n ", index, fpga); in print_hydra_version()
82 fpga = pci_map_bar(devno, PCI_BASE_ADDRESS_0, in hydra_initialize()
98 if (!fpga) in do_hydrate()
104 writel(REFL_PATTERN, &fpga->reflection_low); in do_hydrate()
105 res = readl(&fpga->reflection_low); in do_hydrate()
109 writel(REFL_PATTERN_INV, &fpga->reflection_low); in do_hydrate()
[all …]
/rk3399_rockchip-uboot/cmd/
H A Dfpgad.c32 unsigned int fpga; in do_fpga_md() local
42 fpga = dp_last_fpga; in do_fpga_md()
53 fpga = simple_strtoul(argv[1], NULL, 16); in do_fpga_md()
74 fpga_get_reg(fpga, in do_fpga_md()
75 (u16 *)fpga_ptr[fpga] + addr in do_fpga_md()
91 dp_last_fpga = fpga; in do_fpga_md()
/rk3399_rockchip-uboot/doc/uImage.FIT/
H A Dmulti-with-fpga.its9 description = "Configuration to load fpga before Kernel";
25 fpga@1 {
28 type = "fpga";
61 description = "Linux with fpga";
64 fpga = "fpga@1";
/rk3399_rockchip-uboot/board/gdsys/mpc8308/
H A Dhrcon.c61 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data) in fpga_set_reg() argument
65 switch (fpga) { in fpga_set_reg()
70 res = mclink_send(fpga - 1, regoff, data); in fpga_set_reg()
82 int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data) in fpga_get_reg() argument
86 switch (fpga) { in fpga_get_reg()
91 if (fpga > mclink_fpgacount) in fpga_get_reg()
93 res = mclink_receive(fpga - 1, regoff, data); in fpga_get_reg()
295 int mpc8308_get_fpga_done(unsigned fpga) in mpc8308_get_fpga_done() argument
373 unsigned fpga; member
392 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); in mii_mdio_active()
[all …]
H A Dstrider.c64 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data) in fpga_set_reg() argument
68 switch (fpga) { in fpga_set_reg()
73 res = mclink_send(fpga - 1, regoff, data); in fpga_set_reg()
85 int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data) in fpga_get_reg() argument
89 switch (fpga) { in fpga_get_reg()
94 if (fpga > mclink_fpgacount) in fpga_get_reg()
96 res = mclink_receive(fpga - 1, regoff, data); in fpga_get_reg()
350 int mpc8308_get_fpga_done(unsigned fpga) in mpc8308_get_fpga_done() argument
428 unsigned fpga; member
447 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); in mii_mdio_active()
[all …]
H A Dmpc8308.h8 int mpc8308_get_fpga_done(unsigned fpga);
/rk3399_rockchip-uboot/board/gdsys/p1022/
H A Dcontrolcenterd.c361 struct ihs_fpga *fpga; in hydra_initialize() local
386 fpga = pci_map_bar(devno, PCI_BASE_ADDRESS_0, in hydra_initialize()
390 writel(1, &fpga->control); in hydra_initialize()
392 versions = readl(&fpga->versions); in hydra_initialize()
393 fpga_version = readl(&fpga->fpga_version); in hydra_initialize()
394 fpga_features = readl(&fpga->fpga_features); in hydra_initialize()
/rk3399_rockchip-uboot/board/astro/mcf5373l/
H A DMakefile8 obj-y = mcf5373l.o fpga.o
/rk3399_rockchip-uboot/board/theadorable/
H A DMakefile8 obj-y += fpga.o
/rk3399_rockchip-uboot/board/armadeus/apf27/
H A DMakefile12 obj-$(CONFIG_FPGA) += fpga.o
H A Dfpga.c45 xilinx_desc fpga[CONFIG_FPGA_COUNT] = { variable
221 fpga_add(fpga_xilinx, &fpga[i]); in APF27_init_fpga()
/rk3399_rockchip-uboot/board/spear/x600/
H A DMakefile12 obj-y := fpga.o x600.o
H A Dfpga.c176 static xilinx_desc fpga[CONFIG_FPGA_COUNT] = { variable
261 fpga_add(fpga_xilinx, &fpga[0]); in x600_init_fpga()
/rk3399_rockchip-uboot/board/teejet/mt_ventoux/
H A Dmt_ventoux.c203 xilinx_desc fpga = XILINX_XC6SLX4_DESC(slave_serial, variable
216 fpga_add(fpga_xilinx, &fpga); in mt_ventoux_init_fpga()

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