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Searched refs:divn (Results 1 – 9 of 9) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/mach-uniphier/clk/
H A Dpll-base-ld20.c32 unsigned int ssc_rate, unsigned int divn) in uniphier_ld20_sscpll_init() argument
44 tmp |= (487 * freq * ssc_rate / divn / 512) & in uniphier_ld20_sscpll_init()
50 tmp |= (41859 * freq / divn) & SC_PLLCTRL2_SSC_JK_MASK; in uniphier_ld20_sscpll_init()
H A Dpll.h16 unsigned int ssc_rate, unsigned int divn);
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-tegra/
H A Dclock.h62 unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn,
89 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
H A Dwarmboot.h74 u32 divn:10; member
/rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra20/
H A Dwarmboot.c154 u32 divm, divn, divp, cpcon, lfcon; in warmboot_save_sdram_params() local
156 if (clock_ll_read_pll(CLOCK_ID_MEMORY, &divm, &divn, &divp, in warmboot_save_sdram_params()
160 scratch2.pllm_base_divn = divn; in warmboot_save_sdram_params()
H A Dwarmboot_avp.c169 pllx_base.divn = scratch3.pllx_base_divn; in wb_start()
/rk3399_rockchip-uboot/arch/arm/mach-tegra/
H A Dcpu.c171 int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, in pllx_set_rate() argument
189 reg |= (divn << pllinfo->n_shift) | (divp << pllinfo->p_shift); in pllx_set_rate()
203 if (divn > 600) in pllx_set_rate()
H A Dclock.c90 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn, in clock_ll_read_pll() argument
104 *divn = (data >> pllinfo->n_shift) & pllinfo->n_mask; in clock_ll_read_pll()
114 unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn, in clock_start_pll() argument
148 data = (divm << pllinfo->m_shift) | (divn << pllinfo->n_shift); in clock_start_pll()
/rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra124/
H A Dclock.c1067 u32 divm, divn, divp, cpcon; in clock_set_display_rate() local
1094 divn = vco / cf; in clock_set_display_rate()
1095 if (divn >= max_n) in clock_set_display_rate()
1098 diff = vco - divn * cf; in clock_set_display_rate()
1099 if (divn + 1 < max_n && diff > cf / 2) { in clock_set_display_rate()
1100 divn++; in clock_set_display_rate()
1109 best_n = divn; in clock_set_display_rate()