Searched refs:div_sel (Results 1 – 3 of 3) sorted by relevance
107 u32 reg, div_sel; in decode_pll() local124 div_sel = (reg & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >> in decode_pll()127 return (infreq * div_sel) / 2; in decode_pll()167 div_sel = (reg & CCM_ANALOG_PLL_DDR_DIV_SELECT_MASK) >> in decode_pll()170 return infreq * (div_sel + num / denom); in decode_pll()
1368 u32 con, sel, div_sel; in rv1126_gmac_tx_rx_set_clk() local1375 div_sel = RGMII_CLK_DIV50; in rv1126_gmac_tx_rx_set_clk()1377 div_sel = RGMII_CLK_DIV5; in rv1126_gmac_tx_rx_set_clk()1379 div_sel = RGMII_CLK_DIV0; in rv1126_gmac_tx_rx_set_clk()1381 div_sel << RGMII_CLK_SEL_SHIFT); in rv1126_gmac_tx_rx_set_clk()1384 div_sel = RMII_CLK_DIV20; in rv1126_gmac_tx_rx_set_clk()1386 div_sel = RMII_CLK_DIV2; in rv1126_gmac_tx_rx_set_clk()1388 div_sel << RMII_CLK_SEL_SHIFT); in rv1126_gmac_tx_rx_set_clk()
2064 u32 con, sel, div_sel; in rk3568_gmac_tx_rx_set_clk() local2071 div_sel = RGMII0_CLK_SEL_2_5M; in rk3568_gmac_tx_rx_set_clk()2073 div_sel = RGMII0_CLK_SEL_25M; in rk3568_gmac_tx_rx_set_clk()2075 div_sel = RGMII0_CLK_SEL_125M; in rk3568_gmac_tx_rx_set_clk()2078 div_sel << RGMII0_CLK_SEL_SHIFT); in rk3568_gmac_tx_rx_set_clk()2081 div_sel = RMII0_CLK_SEL_2_5M; in rk3568_gmac_tx_rx_set_clk()2083 div_sel = RMII0_CLK_SEL_25M; in rk3568_gmac_tx_rx_set_clk()2086 div_sel << RMII0_CLK_SEL_SHIFT); in rk3568_gmac_tx_rx_set_clk()