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Searched refs:dc (Results 1 – 25 of 37) sorted by relevance

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/rk3399_rockchip-uboot/drivers/video/
H A Dtegra.c44 static void update_window(struct dc_ctlr *dc, struct disp_ctl_win *win) in update_window() argument
49 val = readl(&dc->cmd.disp_win_header); in update_window()
51 writel(val, &dc->cmd.disp_win_header); in update_window()
53 writel(win->fmt, &dc->win.color_depth); in update_window()
55 clrsetbits_le32(&dc->win.byte_swap, BYTE_SWAP_MASK, in update_window()
60 writel(val, &dc->win.pos); in update_window()
64 writel(val, &dc->win.size); in update_window()
68 writel(val, &dc->win.prescaled_size); in update_window()
70 writel(0, &dc->win.h_initial_dda); in update_window()
71 writel(0, &dc->win.v_initial_dda); in update_window()
[all …]
/rk3399_rockchip-uboot/board/sysam/amcore/
H A Damcore.c58 sdramctrl_t *dc = (sdramctrl_t *)(MMAP_DRAMC); in dram_init() local
83 out_be16(&dc->dcr, 0x8200 | RC); in dram_init()
88 out_be32(&dc->dacr0, 0x00003304); in dram_init()
91 out_be32(&dc->dmr0, dramsize|1); in dram_init()
94 out_be32(&dc->dacr0, 0x0000330c); in dram_init()
97 out_be32(&dc->dacr0, 0x0000b304); in dram_init()
101 out_be32(&dc->dacr0, 0x0000b344); in dram_init()
/rk3399_rockchip-uboot/drivers/spi/
H A Dti_qspi.c86 u32 dc; member
114 u32 dc; member
148 priv->dc = 0; in __ti_qspi_set_mode()
150 priv->dc |= QSPI_CKPHA(0); in __ti_qspi_set_mode()
152 priv->dc |= QSPI_CKPOL(0); in __ti_qspi_set_mode()
154 priv->dc |= QSPI_CSPOL(0); in __ti_qspi_set_mode()
161 writel(priv->dc, &priv->base->dc); in __ti_qspi_claim_bus()
165 priv->dc <<= cs * 8; in __ti_qspi_claim_bus()
166 writel(priv->dc, &priv->base->dc); in __ti_qspi_claim_bus()
173 writel(0, &priv->base->dc); in __ti_qspi_release_bus()
[all …]
/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc85xx/
H A Dfsl_corenet2_serdes.c206 u32 pll_num, pll_status, bc, dc, fc, pll_cr_upd, pll_cr0, pll_cr1; in serdes_init() local
244 dc = (sfp_spfr0 >> DC1_SHIFT) & DC_MASK; in serdes_init()
250 dc = (sfp_spfr0 >> DC2_SHIFT) & DC_MASK; in serdes_init()
256 dc = (sfp_spfr0 >> DC1_SHIFT) & DC_MASK; in serdes_init()
278 pll_cr0 | (dc << CR0_DCBIAS_SHIFT)); in serdes_init()
280 pll_num, (pll_cr0 | (dc << CR0_DCBIAS_SHIFT))); in serdes_init()
308 if (dc_status != dc) in serdes_init()
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-s32v234/
H A Dmc_cgm_regs.h21 #define CGM_SC_DCn(cgm_addr,dc) ( ((cgm_addr) + 0x000007E8) + ((dc) * 0x4) ) argument
30 #define CGM_ACn_DCm(cgm_addr,ac,dc) ( ((cgm_addr) + 0x00000808) + ((ac) * 0x20) + ((dc) * 0x4) ) argument
/rk3399_rockchip-uboot/arch/arm/cpu/armv8/
H A Dcache.S52 dc isw, x9
54 1: dc cisw, x9 /* clean & invalidate by set/way */
144 1: dc civac, x0 /* clean & invalidate data or unified cache */
171 1: dc ivac, x0 /* invalidate data or unified cache */
/rk3399_rockchip-uboot/doc/device-tree-bindings/video/
H A Dtegra20-dc.txt12 - compatible : Should be "nvidia,tegra20-dc"
53 dc@54200000 {
54 compatible = "nvidia,tegra20-dc";
/rk3399_rockchip-uboot/arch/arm/dts/
H A Dtegra20-u-boot.dtsi4 dc@54200000 {
H A Dtegra124-nyan-big-u-boot.dtsi11 dc@54200000 {
H A Dtegra114.dtsi44 dc@54200000 {
45 compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
50 clock-names = "dc", "parent";
52 reset-names = "dc";
63 dc@54240000 {
64 compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
69 clock-names = "dc", "parent";
71 reset-names = "dc";
H A Dtegra20-medcom-wide.dts25 dc@54200000 {
H A Dtegra20-tec.dts25 dc@54200000 {
H A Dtegra20.dtsi79 dc@54200000 {
80 compatible = "nvidia,tegra20-dc";
85 clock-names = "dc", "parent";
87 reset-names = "dc";
96 dc@54240000 {
97 compatible = "nvidia,tegra20-dc";
102 clock-names = "dc", "parent";
104 reset-names = "dc";
H A Dtegra30.dtsi160 dc@54200000 {
161 compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc";
166 clock-names = "dc", "parent";
168 reset-names = "dc";
179 dc@54240000 {
180 compatible = "nvidia,tegra30-dc";
185 clock-names = "dc", "parent";
187 reset-names = "dc";
H A Dtegra210.dtsi119 dc@54200000 {
120 compatible = "nvidia,tegra210-dc";
125 clock-names = "dc", "parent";
127 reset-names = "dc";
134 dc@54240000 {
135 compatible = "nvidia,tegra210-dc";
140 clock-names = "dc", "parent";
142 reset-names = "dc";
H A Dtegra124.dtsi97 dc@54200000 {
98 compatible = "nvidia,tegra124-dc";
103 clock-names = "dc", "parent";
105 reset-names = "dc";
112 dc@54240000 {
113 compatible = "nvidia,tegra124-dc";
118 clock-names = "dc", "parent";
120 reset-names = "dc";
H A Dtegra20-colibri.dts24 dc@54200000 {
H A Dexynos5420-smdk5420.dts36 samsung,dc-value = <25>;
H A Ddm816x-clocks.dtsi179 mpu_ck: mpu_ck@15dc {
H A Dexynos5800-peach-pi.dts71 samsung,dc-value = <25>;
H A Dexynos5250-smdk5250.dts86 samsung,dc-value = <25>;
/rk3399_rockchip-uboot/doc/device-tree-bindings/gpu/
H A Dnvidia,tegra20-host1x.txt105 - dc: display controller
108 - compatible: "nvidia,tegra<chip>-dc"
114 - dc
120 - dc
309 dc@54200000 {
310 compatible = "nvidia,tegra20-dc";
315 clock-names = "dc", "parent";
317 reset-names = "dc";
324 dc@54240000 {
325 compatible = "nvidia,tegra20-dc";
[all …]
/rk3399_rockchip-uboot/doc/device-tree-bindings/exynos/
H A Dtmu.txt25 - samsung,dc-value : Measured data calibration value (Constant 25)
43 samsung,dc-value = <25>;
/rk3399_rockchip-uboot/board/hisilicon/hikey/
H A Dbuild-tf.mak4 makethreads := $(shell dc -e "$(makejobs) 1 + p")
/rk3399_rockchip-uboot/board/freescale/s32v234evb/
H A Dclock.c166 static void aux_div_clk_config(uintptr_t cgm_addr, u8 ac, u8 dc, u32 divider) in aux_div_clk_config() argument
170 CGM_ACn_DCm(cgm_addr, ac, dc)); in aux_div_clk_config()

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