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Searched refs:cycles (Results 1 – 25 of 35) sorted by relevance

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/rk3399_rockchip-uboot/cmd/
H A Dtime.c9 static void report_time(ulong cycles) in report_time() argument
14 total_seconds = cycles / CONFIG_SYS_HZ; in report_time()
15 remainder = cycles % CONFIG_SYS_HZ; in report_time()
29 ulong cycles = 0; in do_time() local
36 retval = cmd_process(0, argc - 1, argv + 1, &repeatable, &cycles); in do_time()
37 report_time(cycles); in do_time()
/rk3399_rockchip-uboot/arch/xtensa/lib/
H A Dtime.c25 static void delay_cycles(unsigned cycles) in delay_cycles() argument
28 unsigned expiry = get_ccount() + cycles; in delay_cycles()
40 for (i = cycles >> 4U; i > 0; --i) in delay_cycles()
42 fake_ccount += cycles; in delay_cycles()
/rk3399_rockchip-uboot/board/keymile/km_arm/
H A Dkwbimage_256M8_1.cfg120 DATA 0xFFD01408 0x2202444E # DDR Timing (Low) (active cycles value +1)
121 # bit 3-0: 0xe, TRAS = 45ns -> 15 clk cycles
122 # bit 7-4: 0x4, TRCD = 15ns -> 5 clk cycles
123 # bit 11-8: 0x4, TRP = 15ns -> 5 clk cycles
124 # bit 15-12: 0x4, TWR = 15ns -> 5 clk cycles
125 # bit 19-16: 0x2, TWTR = 7,5ns -> 3 clk cycles
128 # bit 27-24: 0x2, TRRD = 7,5ns -> 3 clk cycles
129 # bit 31-28: 0x2, TRTP = 7,5ns -> 3 clk cycles
132 # bit 6-0: 0x3E, TRFC = 195ns -> 63 clk cycles
198 # bit 7-4: 2, M_ODT assertion 2 cycles after read start command
[all …]
H A Dkwbimage-memphis.cfg67 DATA 0xFFD01408 0x2302433E # DDR Timing (Low) (active cycles value +1)
135 # bit7-4 : 0010, M_ODT assertion 2 cycles after read
136 # bit11-8 : 0101, M_ODT de-assertion 5 cycles after read
137 # bit15-12: 0100, internal ODT assertion 4 cycles after read
138 # bit19-16: 1000, internal ODT de-assertion 8 cycles after read
143 # bit7-4 : 0101, M_ODT de-assertion x cycles after write
144 # bit11-8 : 0100, internal ODT assertion x cycles after write
145 # bit15-12: 1000, internal ODT de-assertion x cycles after write
H A Dkwbimage_128M16_1.cfg118 DATA 0xFFD01408 0x2302444e # DDR Timing (Low) (active cycles value +1)
196 # bit 7-4: 2, M_ODT assertion 2 cycles after read start command
197 # bit 11-8: 5, M_ODT de-assertion 5 cycles after read start command
198 # (ODT turn off delay 2,5 clk cycles)
208 # bit 11-8: 4, internal ODT assertion 2 cycles after write start command
210 # bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command
H A Dkwbimage.cfg64 DATA 0xFFD01408 0x34136552 # DDR Timing (Low) (active cycles value +1)
/rk3399_rockchip-uboot/board/buffalo/lsxl/
H A Dkwbimage-lsxhl.cfg40 # bit4: 1, T2 mode, addr/cmd are driven for two cycles
141 # bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
142 # bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal
143 # bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
144 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
149 # bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
150 # bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
151 # bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
152 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
H A Dkwbimage-lschl.cfg141 # bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
142 # bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal
143 # bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
144 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
149 # bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
150 # bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
151 # bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
152 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
/rk3399_rockchip-uboot/board/d-link/dns325/
H A Dkwbimage.cfg130 # bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
131 # bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal
132 # bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
133 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
137 # bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
138 # bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
139 # bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
140 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
/rk3399_rockchip-uboot/arch/arm/dts/
H A Domap36xx.dtsi54 ti,clock-cycles = <8>;
/rk3399_rockchip-uboot/doc/device-tree-bindings/clock/
H A Drockchip,rk3288-dmc.txt25 …f the NIF is idle in Access state for auto-self-refresh-cnt * 32 * n_clk cycles.The automatic self…
26 …ed into power-down mode if the NIF is idle for auto-power-down-cnt n_clk cycles.The automatic powe…
/rk3399_rockchip-uboot/board/Seagate/nas220/
H A Dkwbimage.cfg46 DATA 0xFFD01408 0x11012227 # DDR Timing (Low) (active cycles value +1)
/rk3399_rockchip-uboot/board/Marvell/guruplug/
H A Dkwbimage.cfg43 DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
/rk3399_rockchip-uboot/board/Seagate/dockstar/
H A Dkwbimage.cfg46 DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
/rk3399_rockchip-uboot/board/Synology/ds109/
H A Dkwbimage.cfg47 DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
/rk3399_rockchip-uboot/board/Marvell/dreamplug/
H A Dkwbimage.cfg44 DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
/rk3399_rockchip-uboot/board/Seagate/goflexhome/
H A Dkwbimage.cfg49 DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
/rk3399_rockchip-uboot/board/Marvell/sheevaplug/
H A Dkwbimage.cfg43 DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
/rk3399_rockchip-uboot/board/LaCie/netspace_v2/
H A Dkwbimage.cfg44 DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
H A Dkwbimage-is2.cfg44 DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
H A Dkwbimage-ns2l.cfg44 DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
/rk3399_rockchip-uboot/board/cloudengines/pogo_e02/
H A Dkwbimage.cfg47 DATA 0xffd01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
/rk3399_rockchip-uboot/board/raidsonic/ib62x0/
H A Dkwbimage.cfg44 DATA 0xffd01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
/rk3399_rockchip-uboot/board/LaCie/net2big_v2/
H A Dkwbimage.cfg44 DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
/rk3399_rockchip-uboot/board/Marvell/openrd/
H A Dkwbimage.cfg43 DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)

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