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/rk3399_rockchip-uboot/arch/arm/dts/
H A Dam33xx-clocks.dtsi2 * Device Tree Source for AM33xx clock data
12 #clock-cells = <0>;
13 compatible = "ti,mux-clock";
20 #clock-cells = <0>;
21 compatible = "fixed-factor-clock";
23 clock-mult = <1>;
24 clock-div = <1>;
28 #clock-cells = <0>;
29 compatible = "fixed-factor-clock";
31 clock-mult = <1>;
[all …]
H A Dam43xx-clocks.dtsi2 * Device Tree Source for AM43xx clock data
12 #clock-cells = <0>;
13 compatible = "ti,mux-clock";
20 #clock-cells = <0>;
21 compatible = "ti,mux-clock";
28 #clock-cells = <0>;
29 compatible = "ti,mux-clock";
36 #clock-cells = <0>;
37 compatible = "fixed-factor-clock";
39 clock-mult = <1>;
[all …]
H A Domap3xxx-clocks.dtsi2 * Device Tree Source for OMAP3 clock data
12 #clock-cells = <0>;
13 compatible = "fixed-clock";
14 clock-frequency = <16800000>;
18 #clock-cells = <0>;
19 compatible = "ti,mux-clock";
25 #clock-cells = <0>;
26 compatible = "ti,divider-clock";
35 #clock-cells = <0>;
36 compatible = "ti,gate-clock";
[all …]
H A Dkeystone-clocks.dtsi2 * Device Tree Source for Keystone 2 clock tree
17 #clock-cells = <0>;
18 compatible = "ti,keystone,pll-mux-clock";
23 clock-output-names = "mainmuxclk";
27 #clock-cells = <0>;
28 compatible = "fixed-factor-clock";
30 clock-div = <1>;
31 clock-mult = <1>;
32 clock-output-names = "chipclk1";
36 #clock-cells = <0>;
[all …]
H A Ddra7xx-clocks.dtsi2 * Device Tree Source for DRA7xx clock data
12 #clock-cells = <0>;
13 compatible = "ti,dra7-atl-clock";
18 #clock-cells = <0>;
19 compatible = "ti,dra7-atl-clock";
24 #clock-cells = <0>;
25 compatible = "ti,dra7-atl-clock";
30 #clock-cells = <0>;
31 compatible = "ti,dra7-atl-clock";
36 #clock-cells = <0>;
[all …]
H A Domap36xx-omap3430es2plus-clocks.dtsi2 * Device Tree Source for OMAP34xx/OMAP36xx clock data
12 #clock-cells = <0>;
13 compatible = "ti,composite-no-wait-gate-clock";
20 #clock-cells = <0>;
21 compatible = "ti,composite-divider-clock";
29 #clock-cells = <0>;
30 compatible = "ti,composite-clock";
35 #clock-cells = <0>;
36 compatible = "fixed-factor-clock";
38 clock-mult = <1>;
[all …]
H A Ddm816x-clocks.dtsi9 #clock-cells = <1>;
10 compatible = "ti,dm816-fapll-clock";
13 clock-indices = <1>, <2>, <3>, <4>, <5>,
15 clock-output-names = "main_pll_clk1",
25 #clock-cells = <1>;
26 compatible = "ti,dm816-fapll-clock";
29 clock-indices = <1>, <2>, <3>, <4>;
30 clock-output-names = "ddr_pll_clk1",
37 #clock-cells = <1>;
38 compatible = "ti,dm816-fapll-clock";
[all …]
H A Dkeystone-k2hk-clocks.dtsi4 * Keystone 2 Kepler/Hawking SoC clock nodes
13 #clock-cells = <0>;
14 compatible = "ti,keystone,pll-clock";
16 clock-output-names = "arm-pll-clk";
22 #clock-cells = <0>;
23 compatible = "ti,keystone,main-pll-clock";
30 #clock-cells = <0>;
31 compatible = "ti,keystone,pll-clock";
33 clock-output-names = "papllclk";
39 #clock-cells = <0>;
[all …]
H A Domap36xx-am35xx-omap3430es2plus-clocks.dtsi2 * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data
12 #clock-cells = <0>;
13 compatible = "fixed-factor-clock";
15 clock-mult = <1>;
16 clock-div = <3>;
20 #clock-cells = <0>;
21 compatible = "fixed-factor-clock";
23 clock-mult = <1>;
24 clock-div = <5>;
29 #clock-cells = <0>;
[all …]
H A Dkeystone-k2l-clocks.dtsi4 * Keystone 2 lamarr SoC clock nodes
13 #clock-cells = <0>;
14 compatible = "ti,keystone,pll-clock";
16 clock-output-names = "arm-pll-clk";
22 #clock-cells = <0>;
23 compatible = "ti,keystone,main-pll-clock";
30 #clock-cells = <0>;
31 compatible = "ti,keystone,pll-clock";
33 clock-output-names = "papllclk";
39 #clock-cells = <0>;
[all …]
H A Domap34xx-omap36xx-clocks.dtsi2 * Device Tree Source for OMAP34XX/OMAP36XX clock data
12 #clock-cells = <0>;
13 compatible = "fixed-factor-clock";
15 clock-mult = <1>;
16 clock-div = <1>;
20 #clock-cells = <0>;
21 compatible = "ti,omap3-interface-clock";
28 #clock-cells = <0>;
29 compatible = "ti,omap3-interface-clock";
36 #clock-cells = <0>;
[all …]
H A Dzynqmp-clk.dtsi13 compatible = "fixed-clock";
14 #clock-cells = <0>;
15 clock-frequency = <100000000>;
20 compatible = "fixed-clock";
21 #clock-cells = <0>;
22 clock-frequency = <125000000>;
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <200000000>;
32 compatible = "fixed-clock";
[all …]
H A Dsama5d2.dtsi16 compatible = "fixed-clock";
17 #clock-cells = <0>;
18 clock-frequency = <0>;
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
24 clock-frequency = <0>;
38 clock-names = "ohci_clk", "hclk", "uhpck";
46 clock-names = "usb_clk", "ehci_clk";
54 clock-names = "hclock", "multclk", "baseclk";
62 clock-names = "hclock", "multclk", "baseclk";
[all …]
H A Dzynqmp-ep108-clk.dtsi2 * clock specification for Xilinx ZynqMP ep108 development board
13 compatible = "fixed-clock";
14 #clock-cells = <0>;
15 clock-frequency = <25000000>;
20 compatible = "fixed-clock";
21 #clock-cells = <0x0>;
22 clock-frequency = <111111111>;
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <75000000>;
[all …]
H A Dkeystone-k2e-clocks.dtsi13 #clock-cells = <0>;
14 compatible = "ti,keystone,main-pll-clock";
21 #clock-cells = <0>;
22 compatible = "ti,keystone,pll-clock";
24 clock-output-names = "papllclk";
30 #clock-cells = <0>;
31 compatible = "ti,keystone,pll-clock";
33 clock-output-names = "ddr-3a-pll-clk";
39 #clock-cells = <0>;
40 compatible = "ti,keystone,psc-clock";
[all …]
H A Dstih410-clock.dtsi8 #include <dt-bindings/clock/stih410-clks.h>
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
23 clock-frequency = <30000000>;
24 clock-output-names = "CLK_SYSIN";
28 * ARM Peripheral clock for timers
31 #clock-cells = <0>;
32 compatible = "fixed-factor-clock";
34 clock-div = <2>;
35 clock-mult = <1>;
[all …]
H A Dstih407-clock.dtsi8 #include <dt-bindings/clock/stih407-clks.h>
19 #clock-cells = <0>;
20 compatible = "fixed-clock";
21 clock-frequency = <30000000>;
25 * ARM Peripheral clock for timers
28 #clock-cells = <0>;
29 compatible = "fixed-factor-clock";
32 clock-div = <2>;
33 clock-mult = <1>;
44 #clock-cells = <1>;
[all …]
H A Domap36xx-clocks.dtsi2 * Device Tree Source for OMAP36xx clock data
12 #clock-cells = <0>;
13 compatible = "ti,omap3-dpll-per-j-type-clock";
19 #clock-cells = <0>;
20 compatible = "ti,hsdiv-gate-clock";
29 #clock-cells = <0>;
30 compatible = "ti,hsdiv-gate-clock";
38 #clock-cells = <0>;
39 compatible = "ti,hsdiv-gate-clock";
47 #clock-cells = <0>;
[all …]
H A Dexynos7420.dtsi12 #include <dt-bindings/clock/exynos7420-clk.h>
17 compatible = "fixed-clock";
18 clock-output-names = "fin_pll";
20 #clock-cells = <0>;
23 clock_topc: clock-controller@10570000 {
24 compatible = "samsung,exynos7-clock-topc";
27 #clock-cells = <1>;
29 clock-names = "fin_pll";
32 clock_top0: clock-controller@105d0000 {
33 compatible = "samsung,exynos7-clock-top0";
[all …]
H A Dimx7ulp.dtsi9 #include <dt-bindings/clock/imx7ulp-clock.h>
80 ckil: clock@0 {
81 compatible = "fixed-clock";
82 #clock-cells = <0>;
83 clock-frequency = <32768>;
84 clock-output-names = "ckil";
87 osc: clock@1 {
88 compatible = "fixed-clock";
89 #clock-cells = <0>;
90 clock-frequency = <24000000>;
[all …]
H A Dsun5i.dtsi47 #include <dt-bindings/clock/sun4i-a10-pll2.h>
72 * This is a dummy clock, to be used as placeholder on
73 * other mux clocks when a specific parent clock is not
78 #clock-cells = <0>;
79 compatible = "fixed-clock";
80 clock-frequency = <0>;
84 #clock-cells = <0>;
87 clock-frequency = <24000000>;
88 clock-output-names = "osc24M";
92 compatible = "fixed-factor-clock";
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-socfpga/
H A Dclock_manager_gen5.c322 u32 reg, clock; in cm_get_main_vco_clk_hz() local
326 clock = cm_get_osc_clk_hz(1); in cm_get_main_vco_clk_hz()
327 clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >> in cm_get_main_vco_clk_hz()
329 clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >> in cm_get_main_vco_clk_hz()
332 return clock; in cm_get_main_vco_clk_hz()
337 u32 reg, clock = 0; in cm_get_per_vco_clk_hz() local
344 clock = cm_get_osc_clk_hz(1); in cm_get_per_vco_clk_hz()
346 clock = cm_get_osc_clk_hz(2); in cm_get_per_vco_clk_hz()
348 clock = cm_get_f2s_per_ref_clk_hz(); in cm_get_per_vco_clk_hz()
352 clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >> in cm_get_per_vco_clk_hz()
[all …]
/rk3399_rockchip-uboot/drivers/clk/at91/
H A DKconfig2 bool "AT91 clock drivers"
6 This option is used to enable the AT91 clock driver.
7 The driver supports the AT91 clock generator, including
8 the oscillators and PLLs, such as main clock, slow clock,
9 PLLA, UTMI PLL. Clocks can also be a source clock of other
10 clocks a tree structure, such as master clock, usb device
11 clock, matrix clock and generic clock.
12 Devices can use a common clock API to request a particular
13 clock, enable it and get its rate.
19 This option is used to enable the AT91 UTMI PLL clock
[all …]
/rk3399_rockchip-uboot/arch/nios2/dts/
H A D10m50_devboard.dts39 clock-frequency = <75000000>;
74 clock-frequency = <50000000>;
136 enet_pll: clock@0 {
138 #clock-cells = <1>;
141 compatible = "fixed-clock";
142 #clock-cells = <0>;
143 clock-frequency = <125000000>;
144 clock-output-names = "enet_pll-c0";
148 compatible = "fixed-clock";
149 #clock-cells = <0>;
[all …]
/rk3399_rockchip-uboot/doc/device-tree-bindings/clock/
H A Drockchip,rk3288-cru.txt3 The RK3288 clock controller generates and supplies clock to various
12 - #clock-cells: should be 1.
20 Each clock is assigned an identifier and client nodes can use this identifier
21 to specify the clock which they consume. All available clocks are defined as
22 preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be
29 that they are defined using standard clock bindings with following
30 clock-output-names:
32 - "xin32k" - rtc clock - optional,
33 - "ext_i2s" - external I2S clock - optional,
34 - "ext_hsadc" - external HSADC clock - optional,
[all …]

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