322 	u32 reg, clock;  in cm_get_main_vco_clk_hz()  local
326 	clock = cm_get_osc_clk_hz(1);  in cm_get_main_vco_clk_hz()
327 	clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >>  in cm_get_main_vco_clk_hz()
329 	clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >>  in cm_get_main_vco_clk_hz()
332 	return clock;  in cm_get_main_vco_clk_hz()
337 	u32 reg, clock = 0;  in cm_get_per_vco_clk_hz()  local
344 		clock = cm_get_osc_clk_hz(1);  in cm_get_per_vco_clk_hz()
346 		clock = cm_get_osc_clk_hz(2);  in cm_get_per_vco_clk_hz()
348 		clock = cm_get_f2s_per_ref_clk_hz();  in cm_get_per_vco_clk_hz()
352 	clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >>  in cm_get_per_vco_clk_hz()
354 	clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >>  in cm_get_per_vco_clk_hz()
357 	return clock;  in cm_get_per_vco_clk_hz()
362 	u32 reg, clock;  in cm_get_mpu_clk_hz()  local
364 	clock = cm_get_main_vco_clk_hz();  in cm_get_mpu_clk_hz()
368 	clock /= (reg + 1);  in cm_get_mpu_clk_hz()
370 	clock /= (reg + 1);  in cm_get_mpu_clk_hz()
371 	return clock;  in cm_get_mpu_clk_hz()
376 	u32 reg, clock = 0;  in cm_get_sdram_clk_hz()  local
383 		clock = cm_get_osc_clk_hz(1);  in cm_get_sdram_clk_hz()
385 		clock = cm_get_osc_clk_hz(2);  in cm_get_sdram_clk_hz()
387 		clock = cm_get_f2s_sdr_ref_clk_hz();  in cm_get_sdram_clk_hz()
391 	clock /= ((reg & CLKMGR_SDRPLLGRP_VCO_DENOM_MASK) >>  in cm_get_sdram_clk_hz()
393 	clock *= ((reg & CLKMGR_SDRPLLGRP_VCO_NUMER_MASK) >>  in cm_get_sdram_clk_hz()
400 	clock /= (reg + 1);  in cm_get_sdram_clk_hz()
402 	return clock;  in cm_get_sdram_clk_hz()
407 	u32 reg, clock = 0;  in cm_get_l4_sp_clk_hz()  local
415 		clock = cm_get_main_vco_clk_hz();  in cm_get_l4_sp_clk_hz()
419 		clock /= (reg + 1);  in cm_get_l4_sp_clk_hz()
421 		clock /= (reg + 1);  in cm_get_l4_sp_clk_hz()
423 		clock = cm_get_per_vco_clk_hz();  in cm_get_l4_sp_clk_hz()
427 		clock /= (reg + 1);  in cm_get_l4_sp_clk_hz()
434 	clock = clock / (1 << reg);  in cm_get_l4_sp_clk_hz()
436 	return clock;  in cm_get_l4_sp_clk_hz()
441 	u32 reg, clock = 0;  in cm_get_mmc_controller_clk_hz()  local
449 		clock = cm_get_f2s_per_ref_clk_hz();  in cm_get_mmc_controller_clk_hz()
451 		clock = cm_get_main_vco_clk_hz();  in cm_get_mmc_controller_clk_hz()
455 		clock /= (reg + 1);  in cm_get_mmc_controller_clk_hz()
457 		clock = cm_get_per_vco_clk_hz();  in cm_get_mmc_controller_clk_hz()
461 		clock /= (reg + 1);  in cm_get_mmc_controller_clk_hz()
465 	clock /= 4;  in cm_get_mmc_controller_clk_hz()
466 	return clock;  in cm_get_mmc_controller_clk_hz()
471 	u32 reg, clock = 0;  in cm_get_qspi_controller_clk_hz()  local
479 		clock = cm_get_f2s_per_ref_clk_hz();  in cm_get_qspi_controller_clk_hz()
481 		clock = cm_get_main_vco_clk_hz();  in cm_get_qspi_controller_clk_hz()
485 		clock /= (reg + 1);  in cm_get_qspi_controller_clk_hz()
487 		clock = cm_get_per_vco_clk_hz();  in cm_get_qspi_controller_clk_hz()
491 		clock /= (reg + 1);  in cm_get_qspi_controller_clk_hz()
494 	return clock;  in cm_get_qspi_controller_clk_hz()
499 	u32 reg, clock = 0;  in cm_get_spi_controller_clk_hz()  local
501 	clock = cm_get_per_vco_clk_hz();  in cm_get_spi_controller_clk_hz()
505 	clock /= (reg + 1);  in cm_get_spi_controller_clk_hz()
507 	return clock;  in cm_get_spi_controller_clk_hz()