144303dfaSMichal Simek/* 244303dfaSMichal Simek * clock specification for Xilinx ZynqMP ep108 development board 344303dfaSMichal Simek * 444303dfaSMichal Simek * (C) Copyright 2015, Xilinx, Inc. 544303dfaSMichal Simek * 644303dfaSMichal Simek * Michal Simek <michal.simek@xilinx.com> 744303dfaSMichal Simek * 844303dfaSMichal Simek * SPDX-License-Identifier: GPL-2.0+ 944303dfaSMichal Simek */ 1044303dfaSMichal Simek 1144303dfaSMichal Simek&amba { 1244303dfaSMichal Simek misc_clk: misc_clk { 1344303dfaSMichal Simek compatible = "fixed-clock"; 1444303dfaSMichal Simek #clock-cells = <0>; 1544303dfaSMichal Simek clock-frequency = <25000000>; 16a9022b01SMichal Simek u-boot,dm-pre-reloc; 1744303dfaSMichal Simek }; 1844303dfaSMichal Simek 1944303dfaSMichal Simek i2c_clk: i2c_clk { 2044303dfaSMichal Simek compatible = "fixed-clock"; 2144303dfaSMichal Simek #clock-cells = <0x0>; 2244303dfaSMichal Simek clock-frequency = <111111111>; 2344303dfaSMichal Simek }; 2444303dfaSMichal Simek 2544303dfaSMichal Simek sata_clk: sata_clk { 2644303dfaSMichal Simek compatible = "fixed-clock"; 2744303dfaSMichal Simek #clock-cells = <0>; 2844303dfaSMichal Simek clock-frequency = <75000000>; 2944303dfaSMichal Simek }; 3044303dfaSMichal Simek 3144303dfaSMichal Simek dp_aclk: clock0 { 3244303dfaSMichal Simek compatible = "fixed-clock"; 3344303dfaSMichal Simek #clock-cells = <0>; 3444303dfaSMichal Simek clock-frequency = <50000000>; 3544303dfaSMichal Simek clock-accuracy = <100>; 3644303dfaSMichal Simek }; 3744303dfaSMichal Simek 38e9b2a722SVNSL Durga clk100: clk100 { 39e9b2a722SVNSL Durga compatible = "fixed-clock"; 40e9b2a722SVNSL Durga #clock-cells = <0>; 41e9b2a722SVNSL Durga clock-frequency = <100000000>; 42e9b2a722SVNSL Durga }; 43e9b2a722SVNSL Durga 44e9b2a722SVNSL Durga clk600: clk600 { 45e9b2a722SVNSL Durga compatible = "fixed-clock"; 46e9b2a722SVNSL Durga #clock-cells = <0>; 47e9b2a722SVNSL Durga clock-frequency = <600000000>; 48e9b2a722SVNSL Durga }; 49e9b2a722SVNSL Durga 5044303dfaSMichal Simek dp_aud_clk: clock1 { 5144303dfaSMichal Simek compatible = "fixed-clock"; 5244303dfaSMichal Simek #clock-cells = <0>; 5344303dfaSMichal Simek clock-frequency = <22579200>; 5444303dfaSMichal Simek clock-accuracy = <100>; 5544303dfaSMichal Simek }; 5644303dfaSMichal Simek}; 5744303dfaSMichal Simek 5844303dfaSMichal Simek&can0 { 5944303dfaSMichal Simek clocks = <&misc_clk &misc_clk>; 6044303dfaSMichal Simek}; 6144303dfaSMichal Simek 62*01b78c7eSNaga Sureshkumar Relli&can1 { 63*01b78c7eSNaga Sureshkumar Relli clocks = <&misc_clk &misc_clk>; 64*01b78c7eSNaga Sureshkumar Relli}; 65*01b78c7eSNaga Sureshkumar Relli 66e9b2a722SVNSL Durga&fpd_dma_chan1 { 67e9b2a722SVNSL Durga clocks = <&clk600>, <&clk100>; 68e9b2a722SVNSL Durga}; 69e9b2a722SVNSL Durga 70e9b2a722SVNSL Durga&fpd_dma_chan2 { 71e9b2a722SVNSL Durga clocks = <&clk600>, <&clk100>; 72e9b2a722SVNSL Durga}; 73e9b2a722SVNSL Durga 74e9b2a722SVNSL Durga&fpd_dma_chan3 { 75e9b2a722SVNSL Durga clocks = <&clk600>, <&clk100>; 76e9b2a722SVNSL Durga}; 77e9b2a722SVNSL Durga 78e9b2a722SVNSL Durga&fpd_dma_chan4 { 79e9b2a722SVNSL Durga clocks = <&clk600>, <&clk100>; 80e9b2a722SVNSL Durga}; 81e9b2a722SVNSL Durga 82e9b2a722SVNSL Durga&fpd_dma_chan5 { 83e9b2a722SVNSL Durga clocks = <&clk600>, <&clk100>; 84e9b2a722SVNSL Durga}; 85e9b2a722SVNSL Durga 86e9b2a722SVNSL Durga&fpd_dma_chan6 { 87e9b2a722SVNSL Durga clocks = <&clk600>, <&clk100>; 88e9b2a722SVNSL Durga}; 89e9b2a722SVNSL Durga 90e9b2a722SVNSL Durga&fpd_dma_chan7 { 91e9b2a722SVNSL Durga clocks = <&clk600>, <&clk100>; 92e9b2a722SVNSL Durga}; 93e9b2a722SVNSL Durga 94e9b2a722SVNSL Durga&fpd_dma_chan8 { 95e9b2a722SVNSL Durga clocks = <&clk600>, <&clk100>; 96e9b2a722SVNSL Durga}; 97e9b2a722SVNSL Durga 9844303dfaSMichal Simek&gem0 { 9944303dfaSMichal Simek clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>; 10044303dfaSMichal Simek}; 10144303dfaSMichal Simek 10244303dfaSMichal Simek&gpio { 10344303dfaSMichal Simek clocks = <&misc_clk>; 10444303dfaSMichal Simek}; 10544303dfaSMichal Simek 10644303dfaSMichal Simek&i2c0 { 10744303dfaSMichal Simek clocks = <&i2c_clk>; 10844303dfaSMichal Simek}; 10944303dfaSMichal Simek 11044303dfaSMichal Simek&i2c1 { 11144303dfaSMichal Simek clocks = <&i2c_clk>; 11244303dfaSMichal Simek}; 11344303dfaSMichal Simek 11445212027SPunnaiah Choudary Kalluri&nand0 { 11545212027SPunnaiah Choudary Kalluri clocks = <&misc_clk &misc_clk>; 11645212027SPunnaiah Choudary Kalluri}; 11745212027SPunnaiah Choudary Kalluri 11844303dfaSMichal Simek&qspi { 11944303dfaSMichal Simek clocks = <&misc_clk &misc_clk>; 12044303dfaSMichal Simek}; 12144303dfaSMichal Simek 12244303dfaSMichal Simek&sata { 12344303dfaSMichal Simek clocks = <&sata_clk>; 12444303dfaSMichal Simek}; 12544303dfaSMichal Simek 12644303dfaSMichal Simek&sdhci0 { 12744303dfaSMichal Simek clocks = <&misc_clk>, <&misc_clk>; 12844303dfaSMichal Simek}; 12944303dfaSMichal Simek 13044303dfaSMichal Simek&sdhci1 { 13144303dfaSMichal Simek clocks = <&misc_clk>, <&misc_clk>; 13244303dfaSMichal Simek}; 13344303dfaSMichal Simek 13444303dfaSMichal Simek&spi0 { 13544303dfaSMichal Simek clocks = <&misc_clk &misc_clk>; 13644303dfaSMichal Simek}; 13744303dfaSMichal Simek 13844303dfaSMichal Simek&spi1 { 13944303dfaSMichal Simek clocks = <&misc_clk &misc_clk>; 14044303dfaSMichal Simek}; 14144303dfaSMichal Simek 14244303dfaSMichal Simek&uart0 { 14344303dfaSMichal Simek clocks = <&misc_clk &misc_clk>; 14444303dfaSMichal Simek}; 14544303dfaSMichal Simek 14644303dfaSMichal Simek&usb0 { 14744303dfaSMichal Simek clocks = <&misc_clk>, <&misc_clk>; 14844303dfaSMichal Simek}; 14944303dfaSMichal Simek 15044303dfaSMichal Simek&usb1 { 15144303dfaSMichal Simek clocks = <&misc_clk>, <&misc_clk>; 15244303dfaSMichal Simek}; 15344303dfaSMichal Simek 15444303dfaSMichal Simek&watchdog0 { 15544303dfaSMichal Simek clocks= <&misc_clk>; 15644303dfaSMichal Simek}; 15744303dfaSMichal Simek 15844303dfaSMichal Simek&xilinx_drm { 15944303dfaSMichal Simek clocks = <&misc_clk>; 16044303dfaSMichal Simek}; 16144303dfaSMichal Simek 16244303dfaSMichal Simek&xlnx_dp { 16344303dfaSMichal Simek clocks = <&dp_aclk>, <&dp_aud_clk>; 16444303dfaSMichal Simek}; 16544303dfaSMichal Simek 16644303dfaSMichal Simek&xlnx_dp_snd_codec0 { 16744303dfaSMichal Simek clocks = <&dp_aud_clk>; 16844303dfaSMichal Simek}; 16944303dfaSMichal Simek 17044303dfaSMichal Simek&xlnx_dpdma { 17144303dfaSMichal Simek clocks = <&misc_clk>; 17244303dfaSMichal Simek}; 173