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Searched refs:cacheline (Results 1 – 6 of 6) sorted by relevance

/rk3399_rockchip-uboot/drivers/net/fsl-mc/dpio/
H A Dqbman_portal.h129 const uint32_t *cacheline) in qb_attr_code_decode() argument
131 return d32_uint32_t(code->lsoffset, code->width, cacheline[code->word]); in qb_attr_code_decode()
137 uint32_t *cacheline, uint32_t val) in qb_attr_code_encode() argument
139 cacheline[code->word] = in qb_attr_code_encode()
140 r32_uint32_t(code->lsoffset, code->width, cacheline[code->word]) in qb_attr_code_encode()
145 uint64_t *cacheline, uint64_t val) in qb_attr_code_encode_64() argument
147 cacheline[code->word / 2] = val; in qb_attr_code_encode_64()
/rk3399_rockchip-uboot/doc/
H A DREADME.fsl-ddr70 # cacheline interleaving
71 setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline"
152 hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3,ecc=on
/rk3399_rockchip-uboot/include/configs/
H A DT4240QDS.h521 #define CTRL_INTLV_PREFERED cacheline
H A DT4240RDB.h682 #define CTRL_INTLV_PREFERED cacheline
H A DT208xRDB.h204 #define CTRL_INTLV_PREFERED cacheline
H A DT208xQDS.h219 #define CTRL_INTLV_PREFERED cacheline