| /rk3399_rockchip-uboot/tools/ |
| H A D | vybridimage.c | 50 uint8_t bit7 = (byte & (1 << 7)) ? 1 : 0; in vybridimage_sw_ecc() local
54 res |= ((bit7 ^ bit5 ^ bit4 ^ bit2 ^ bit1) << 1); in vybridimage_sw_ecc()
55 res |= ((bit7 ^ bit6 ^ bit5 ^ bit1 ^ bit0) << 2); in vybridimage_sw_ecc()
56 res |= ((bit7 ^ bit4 ^ bit3 ^ bit0) << 3); in vybridimage_sw_ecc()
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| /rk3399_rockchip-uboot/board/buffalo/lsxl/ |
| H A D | kwbimage-lschl.cfg | 58 # bit7-4: 4, 5 cycle tRCD
80 # bit7-6: 0, Cs1size=nonexistent
106 # bit7: 0, (Test Mode) Normal operation
130 # bit7: 0 required (???)
141 # bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
150 # bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
182 # bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM
197 # bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-3
|
| H A D | kwbimage-lsxhl.cfg | 58 # bit7-4: 4, 5 cycle tRCD
80 # bit7-6: 0, Cs1size=nonexistent
106 # bit7: 0, (Test Mode) Normal operation
130 # bit7: 0 required (???)
141 # bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
150 # bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
182 # bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM
197 # bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-3
|
| /rk3399_rockchip-uboot/board/d-link/dns325/ |
| H A D | kwbimage.cfg | 55 # bit7-4: 5, 6 cycle tRCD
75 # bit7-6: 0, Cs1size=nonexistent
98 # bit7: 0, (Test Mode) Normal operation
120 # bit7: 0 required
130 # bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
138 # bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
164 # bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM
177 # bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-4
|
| /rk3399_rockchip-uboot/board/keymile/km_arm/ |
| H A D | kwbimage-memphis.cfg | 69 # bit7-4: TRCD
89 # bit7-6: 00, Cs1size =nonexistent
125 # bit7 : 0
135 # bit7-4 : 0010, M_ODT assertion 2 cycles after read
143 # bit7-4 : 0101, M_ODT de-assertion x cycles after write
170 # bit7-4: 0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0
|
| H A D | kwbimage.cfg | 66 # bit7-4: TRCD
86 # bit7-6: 00, Cs1size =nonexistent
122 # bit7 : 0
155 # bit7-4: 0, ODT0Wr, Internal ODT asserted during write to DRAM bank0
|
| /rk3399_rockchip-uboot/board/LaCie/netspace_v2/ |
| H A D | kwbimage.cfg | 45 # bit7-4: TRCD
65 # bit7-6: 00, Cs1size =nonexistent
88 # bit7: 0, TestMode=0 normal
110 # bit7 : 1 , D2P Latency enabled
144 # bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
|
| H A D | kwbimage-is2.cfg | 45 # bit7-4: TRCD
65 # bit7-6: 00, Cs1size =nonexistent
88 # bit7: 0, TestMode=0 normal
110 # bit7 : 1 , D2P Latency enabled
144 # bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
|
| H A D | kwbimage-ns2l.cfg | 45 # bit7-4: TRCD
65 # bit7-6: 00, Cs1size =nonexistent
88 # bit7: 0, TestMode=0 normal
110 # bit7 : 1 , D2P Latency enabled
144 # bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
|
| /rk3399_rockchip-uboot/board/cloudengines/pogo_e02/ |
| H A D | kwbimage.cfg | 49 # bit7-4: TRCD
69 # bit7-6: 11, Cs1size=1Gb
92 # bit7: 0, TestMode=0 normal
114 # bit7 : 0
141 # bit7-4: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
|
| /rk3399_rockchip-uboot/board/raidsonic/ib62x0/ |
| H A D | kwbimage.cfg | 46 # bit7-4: TRCD
66 # bit7-6: 11, Cs1size (1Gb)
89 # bit7: 0x0, TestMode=0 normal
111 # bit7: 0x0,
138 # bit7-4: ODT0Rd, MODT[0] asserted during read from DRAM CS0
|
| /rk3399_rockchip-uboot/board/LaCie/net2big_v2/ |
| H A D | kwbimage.cfg | 45 # bit7-4: TRCD
65 # bit7-6: 00, Cs1size =nonexistent
88 # bit7: 0, TestMode=0 normal
110 # bit7 : 1 , D2P Latency enabled
144 # bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
|
| /rk3399_rockchip-uboot/board/Marvell/openrd/ |
| H A D | kwbimage.cfg | 45 # bit7-4: TRCD
65 # bit7-6: 11, Cs1size=1Gb
88 # bit7: 0, TestMode=0 normal
110 # bit7 : 0
137 # bit7-4: 0001, (read) M_ODT[1] is asserted during read from DRAM CS0
|
| /rk3399_rockchip-uboot/board/iomega/iconnect/ |
| H A D | kwbimage.cfg | 45 # bit7-4: TRCD
65 # bit7-6: 11, Cs1size (1Gb)
88 # bit7: 0x0, TestMode=0 normal
110 # bit7: 0x0,
137 # bit7-4: ODT0Rd, MODT[0] asserted during read from DRAM CS0
|
| /rk3399_rockchip-uboot/board/Seagate/nas220/ |
| H A D | kwbimage.cfg | 47 # bit7-4: TRCD
68 # bit7-6: 00, Cs1size =nonexistent
91 # bit7: 0, TestMode=0 normal
114 # bit7 : 0
|
| /rk3399_rockchip-uboot/board/Marvell/guruplug/ |
| H A D | kwbimage.cfg | 45 # bit7-4: TRCD
65 # bit7-6: 10, Cs1size=1Gb
88 # bit7: 0, TestMode=0 normal
110 # bit7 : 0
|
| /rk3399_rockchip-uboot/board/Seagate/dockstar/ |
| H A D | kwbimage.cfg | 48 # bit7-4: TRCD
68 # bit7-6: 00, Cs1size =nonexistent
91 # bit7: 0, TestMode=0 normal
113 # bit7 : 0
|
| /rk3399_rockchip-uboot/board/Synology/ds109/ |
| H A D | kwbimage.cfg | 49 # bit7-4: TRCD
69 # bit7-6: 10, Cs1size=1Gb
92 # bit7: 0, TestMode=0 normal
114 # bit7 : 0
|
| /rk3399_rockchip-uboot/board/Marvell/dreamplug/ |
| H A D | kwbimage.cfg | 46 # bit7-4: TRCD
66 # bit7-6: 10, Cs1size=1Gb
89 # bit7: 0, TestMode=0 normal
111 # bit7 : 0
|
| /rk3399_rockchip-uboot/board/Seagate/goflexhome/ |
| H A D | kwbimage.cfg | 51 # bit7-4: TRCD
71 # bit7-6: 00, Cs1size =nonexistent
94 # bit7: 0, TestMode=0 normal
116 # bit7 : 0
|
| /rk3399_rockchip-uboot/board/Marvell/sheevaplug/ |
| H A D | kwbimage.cfg | 45 # bit7-4: TRCD
65 # bit7-6: 11, Cs1size=1Gb
88 # bit7: 0, TestMode=0 normal
110 # bit7 : 0
|