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Searched refs:bit3 (Results 1 – 21 of 21) sorted by relevance

/rk3399_rockchip-uboot/board/d-link/dns325/
H A Dkwbimage.cfg37 # bit3-0: 0 required
54 # bit3-0: 1, 18 cycle tRAS (tRAS[3-0])
73 # bit3-2: 3, Cs0size=1Gb
91 # bit3-0: 0, Cmd=Normal SDRAM Mode
96 # bit3: 0, Burst Type (0 required)
118 # bit3: 1, MBUS Burst Chop disabled
129 # bit3-0: 0 required
137 # bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
147 # bit3-2: 0x0, CS0 hit selected
155 # bit3-2: 1, CS1 hit selected
[all …]
/rk3399_rockchip-uboot/board/buffalo/lsxl/
H A Dkwbimage-lschl.cfg39 # bit3-0: 0 required
57 # bit3-0: 0xf, 16 cycle tRAS (tRAS[3-0])
78 # bit3-2: 2, Cs0size=512Mbit
98 # bit3-0: 0, Cmd=Normal SDRAM Mode
104 # bit3: 0, Burst Type (0 required)
128 # bit3: 1, MBUS Burst Chop disabled
140 # bit3-0: 0 required
149 # bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
163 # bit3-2: 0x0, CS0 hit selected
181 # bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM
[all …]
H A Dkwbimage-lsxhl.cfg39 # bit3-0: 0 required
57 # bit3-0: 0x1, 18 cycle tRAS (tRAS[3-0])
78 # bit3-2: 3, Cs0size=1Gbit
98 # bit3-0: 0, Cmd=Normal SDRAM Mode
104 # bit3: 0, Burst Type (0 required)
128 # bit3: 1, MBUS Burst Chop disabled
140 # bit3-0: 0 required
149 # bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
163 # bit3-2: 0x0, CS0 hit selected
181 # bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM
[all …]
/rk3399_rockchip-uboot/board/keymile/km_arm/
H A Dkwbimage-memphis.cfg68 # bit3-0: TRAS lsbs
87 # bit3-2: 00, Cs0size=2Gb
105 # bit3-0: 0x0, DDR cmd
123 # bit3 : 1 , MBUS Burst Chop disabled
134 # bit3-0 : 0000, required
142 # bit3-0 : 0001, M_ODT assertion same cycle as write
151 # bit3-2: 00, CS0 hit selected
160 # bit3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0
165 # bit3-2: 00, ODT1 controlled by register
169 # bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
H A Dkwbimage.cfg65 # bit3-0: TRAS lsbs
84 # bit3-2: 11, Cs0size=1Gb
102 # bit3-0: 0x0, DDR cmd
120 # bit3 : 1 , MBUS Burst Chop disabled
136 # bit3-2: 00, CS0 hit selected
145 # bit3-0: 0, ODT0Rd, MODT[0] asserted during read from DRAM CS0
150 # bit3-2: 00, ODT1 controlled by register
154 # bit3-0: F, ODT0Rd, Internal ODT asserted during read from DRAM bank0
/rk3399_rockchip-uboot/tools/
H A Dvybridimage.c46 uint8_t bit3 = (byte & (1 << 3)) ? 1 : 0; in vybridimage_sw_ecc() local
53 res |= ((bit6 ^ bit5 ^ bit3 ^ bit2) << 0); in vybridimage_sw_ecc()
56 res |= ((bit7 ^ bit4 ^ bit3 ^ bit0) << 3); in vybridimage_sw_ecc()
57 res |= ((bit6 ^ bit4 ^ bit3 ^ bit2 ^ bit1 ^ bit0) << 4); in vybridimage_sw_ecc()
/rk3399_rockchip-uboot/board/LaCie/netspace_v2/
H A Dkwbimage.cfg63 # bit3-2: 11, Cs0size=1Gb
81 # bit3-0: 0x0, DDR cmd
86 # bit3: 0, BurstType=0 required
108 # bit3 : 1 , MBUS Burst Chop disabled
125 # bit3-2: 00, CS0 hit selected
134 # bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
139 # bit3-2: 01, ODT1 active NEVER!
143 # bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
H A Dkwbimage-is2.cfg63 # bit3-2: 10, Cs0size=512Mb
81 # bit3-0: 0x0, DDR cmd
86 # bit3: 0, BurstType=0 required
108 # bit3 : 1 , MBUS Burst Chop disabled
125 # bit3-2: 00, CS0 hit selected
134 # bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
139 # bit3-2: 01, ODT1 active NEVER!
143 # bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
H A Dkwbimage-ns2l.cfg63 # bit3-2: 10, Cs0size=512Mb
81 # bit3-0: 0x0, DDR cmd
86 # bit3: 0, BurstType=0 required
108 # bit3 : 1 , MBUS Burst Chop disabled
125 # bit3-2: 00, CS0 hit selected
134 # bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
139 # bit3-2: 01, ODT1 active NEVER!
143 # bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
/rk3399_rockchip-uboot/board/cloudengines/pogo_e02/
H A Dkwbimage.cfg48 # bit3-0: TRAS lsbs
67 # bit3-2: 11, Cs0size=1Gb
85 # bit3-0: 0x0, DDR cmd
90 # bit3: 0, BurstType=0 required
112 # bit3 : 1 , MBUS Burst Chop disabled
129 # bit3-2: 00, CS0 hit selected
140 # bit3-0: 2, ODT0Rd, MODT[0] asserted during read from DRAM CS1
147 # bit3-2: 01, ODT1 active NEVER!
/rk3399_rockchip-uboot/board/raidsonic/ib62x0/
H A Dkwbimage.cfg45 # bit3-0: TRAS lsbs
64 # bit3-2: 11, Cs0size (1Gb)
82 # bit3-0: 0x0, DDR cmd
87 # bit3: 0x0, BurstType=0 required
109 # bit3: 0x1, MBUS Burst Chop disabled
126 # bit3-2: 0x0, CS0 hit selected
137 # bit3-0: ODT0Rd, MODT[0] asserted during read from DRAM CS1
144 # bit3-2: 0x1, ODT1 active NEVER!
/rk3399_rockchip-uboot/board/LaCie/net2big_v2/
H A Dkwbimage.cfg63 # bit3-2: 11, Cs0size=1Gb
81 # bit3-0: 0x0, DDR cmd
86 # bit3: 0, BurstType=0 required
108 # bit3 : 1 , MBUS Burst Chop disabled
125 # bit3-2: 00, CS0 hit selected
134 # bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
139 # bit3-2: 01, ODT1 active NEVER!
143 # bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
/rk3399_rockchip-uboot/board/Marvell/openrd/
H A Dkwbimage.cfg44 # bit3-0: TRAS lsbs
63 # bit3-2: 11, Cs0size=1Gb
81 # bit3-0: 0x0, DDR cmd
86 # bit3: 0, BurstType=0 required
108 # bit3 : 1 , MBUS Burst Chop disabled
125 # bit3-2: 00, CS0 hit selected
136 # bit3-0: 0010, (read) M_ODT[0] is asserted during read from DRAM CS1
143 # bit3-0: 1111, internal ODT is asserted during read from DRAM bank 0-3
/rk3399_rockchip-uboot/board/iomega/iconnect/
H A Dkwbimage.cfg44 # bit3-0: TRAS lsbs
63 # bit3-2: 11, Cs0size (1Gb)
81 # bit3-0: 0x0, DDR cmd
86 # bit3: 0x0, BurstType=0 required
108 # bit3: 0x1, MBUS Burst Chop disabled
125 # bit3-2: 0x0, CS0 hit selected
136 # bit3-0: ODT0Rd, MODT[0] asserted during read from DRAM CS1
143 # bit3-2: 0x1, ODT1 active NEVER!
/rk3399_rockchip-uboot/board/Marvell/guruplug/
H A Dkwbimage.cfg44 # bit3-0: TRAS lsbs
63 # bit3-2: 10, Cs0size=1Gb
81 # bit3-0: 0x0, DDR cmd
86 # bit3: 0, BurstType=0 required
108 # bit3 : 1 , MBUS Burst Chop disabled
125 # bit3-2: 00, CS0 hit selected
138 # bit3-2: 01, ODT1 active NEVER!
/rk3399_rockchip-uboot/board/Seagate/dockstar/
H A Dkwbimage.cfg47 # bit3-0: TRAS lsbs
66 # bit3-2: 11, Cs0size=1Gb
84 # bit3-0: 0x0, DDR cmd
89 # bit3: 0, BurstType=0 required
111 # bit3 : 1 , MBUS Burst Chop disabled
128 # bit3-2: 00, CS0 hit selected
141 # bit3-2: 01, ODT1 active NEVER!
/rk3399_rockchip-uboot/board/Synology/ds109/
H A Dkwbimage.cfg48 # bit3-0: TRAS lsbs
67 # bit3-2: 10, Cs0size=1Gb
85 # bit3-0: 0x0, DDR cmd
90 # bit3: 0, BurstType=0 required
112 # bit3 : 1 , MBUS Burst Chop disabled
129 # bit3-2: 00, CS0 hit selected
144 # bit3-2: 01, ODT1 active NEVER!
/rk3399_rockchip-uboot/board/Marvell/dreamplug/
H A Dkwbimage.cfg45 # bit3-0: TRAS lsbs
64 # bit3-2: 10, Cs0size=1Gb
82 # bit3-0: 0x0, DDR cmd
87 # bit3: 0, BurstType=0 required
109 # bit3 : 1 , MBUS Burst Chop disabled
126 # bit3-2: 00, CS0 hit selected
139 # bit3-2: 01, ODT1 active NEVER!
/rk3399_rockchip-uboot/board/Seagate/goflexhome/
H A Dkwbimage.cfg50 # bit3-0: TRAS lsbs
69 # bit3-2: 11, Cs0size=1Gb
87 # bit3-0: 0x0, DDR cmd
92 # bit3: 0, BurstType=0 required
114 # bit3 : 1 , MBUS Burst Chop disabled
131 # bit3-2: 00, CS0 hit selected
144 # bit3-2: 01, ODT1 active NEVER!
/rk3399_rockchip-uboot/board/Marvell/sheevaplug/
H A Dkwbimage.cfg44 # bit3-0: TRAS lsbs
63 # bit3-2: 11, Cs0size=1Gb
81 # bit3-0: 0x0, DDR cmd
86 # bit3: 0, BurstType=0 required
108 # bit3 : 1 , MBUS Burst Chop disabled
125 # bit3-2: 00, CS0 hit selected
138 # bit3-2: 01, ODT1 active NEVER!
/rk3399_rockchip-uboot/board/Seagate/nas220/
H A Dkwbimage.cfg66 # bit3-2: 11, Cs0size=1Gb
84 # bit3-0: 0x0, DDR cmd
89 # bit3: 0, BurstType=0 required
112 # bit3 : 1 , MBUS Burst Chop disabled
125 # bit3-2: 00, CS0 hit selected
139 # bit3-2: 01, ODT1 active NEVER!