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Searched refs:bit0 (Results 1 – 22 of 22) sorted by relevance

/rk3399_rockchip-uboot/tools/
H A Dvybridimage.c43 uint8_t bit0 = (byte & (1 << 0)) ? 1 : 0; in vybridimage_sw_ecc() local
55 res |= ((bit7 ^ bit6 ^ bit5 ^ bit1 ^ bit0) << 2); in vybridimage_sw_ecc()
56 res |= ((bit7 ^ bit4 ^ bit3 ^ bit0) << 3); in vybridimage_sw_ecc()
57 res |= ((bit6 ^ bit4 ^ bit3 ^ bit2 ^ bit1 ^ bit0) << 4); in vybridimage_sw_ecc()
/rk3399_rockchip-uboot/board/Seagate/nas220/
H A Dkwbimage.cfg80 # bit0: 0, OpenPage enabled
99 # bit0: 0, DDR DLL enabled
123 # bit0: 1, Window enabled
145 #bit0=1, enable DDR init upon this register write
/rk3399_rockchip-uboot/board/Marvell/guruplug/
H A Dkwbimage.cfg77 # bit0: 0, OpenPage enabled
95 # bit0: 0, DDR DLL enabled
123 # bit0: 1, Window enabled
143 #bit0=1, enable DDR init upon this register write
/rk3399_rockchip-uboot/board/Seagate/dockstar/
H A Dkwbimage.cfg80 # bit0: 0, OpenPage enabled
98 # bit0: 0, DDR DLL enabled
126 # bit0: 1, Window enabled
146 #bit0=1, enable DDR init upon this register write
/rk3399_rockchip-uboot/board/Synology/ds109/
H A Dkwbimage.cfg81 # bit0: 0, OpenPage enabled
99 # bit0: 0, DDR DLL enabled
127 # bit0: 1, Window enabled
149 #bit0=1, enable DDR init upon this register write
/rk3399_rockchip-uboot/board/Marvell/dreamplug/
H A Dkwbimage.cfg78 # bit0: 0, OpenPage enabled
96 # bit0: 0, DDR DLL enabled
124 # bit0: 1, Window enabled
144 #bit0=1, enable DDR init upon this register write
/rk3399_rockchip-uboot/board/Seagate/goflexhome/
H A Dkwbimage.cfg83 # bit0: 0, OpenPage enabled
101 # bit0: 0, DDR DLL enabled
129 # bit0: 1, Window enabled
149 #bit0=1, enable DDR init upon this register write
/rk3399_rockchip-uboot/board/Marvell/sheevaplug/
H A Dkwbimage.cfg77 # bit0: 0, OpenPage enabled
95 # bit0: 0, DDR DLL enabled
123 # bit0: 1, Window enabled
143 #bit0=1, enable DDR init upon this register write
/rk3399_rockchip-uboot/board/LaCie/netspace_v2/
H A Dkwbimage.cfg77 # bit0: 0, OpenPage enabled
95 # bit0: 0, DDR DLL enabled
123 # bit0: 1, Window enabled
148 #bit0=1, enable DDR init upon this register write
H A Dkwbimage-is2.cfg77 # bit0: 0, OpenPage enabled
95 # bit0: 0, DDR DLL enabled
123 # bit0: 1, Window enabled
148 #bit0=1, enable DDR init upon this register write
H A Dkwbimage-ns2l.cfg77 # bit0: 0, OpenPage enabled
95 # bit0: 0, DDR DLL enabled
123 # bit0: 1, Window enabled
148 #bit0=1, enable DDR init upon this register write
/rk3399_rockchip-uboot/board/cloudengines/pogo_e02/
H A Dkwbimage.cfg81 # bit0: 0, OpenPage enabled
99 # bit0: 0, DDR DLL enabled
127 # bit0: 1, Window enabled
152 #bit0=1, enable DDR init upon this register write
/rk3399_rockchip-uboot/board/raidsonic/ib62x0/
H A Dkwbimage.cfg78 # bit0: 0, OpenPage enabled
96 # bit0: 0, DDR DLL enabled
124 # bit0: 0x1, Window enabled
149 # bit0: 0x1, enable DDR init upon this register write
/rk3399_rockchip-uboot/board/keymile/km_arm/
H A Dkwbimage.cfg98 # bit0: 0, OpenPage enabled
107 # bit0: 0, DDR DLL enabled
134 # bit0: 1, Window enabled
160 # bit0=1, enable DDR init upon this register write
H A Dkwbimage-memphis.cfg101 # bit0: 0, OpenPage enabled
110 # bit0: 0, DDR DLL enabled
149 # bit0: 1, Window enabled
178 # bit0=1, enable DDR init upon this register write
/rk3399_rockchip-uboot/board/LaCie/net2big_v2/
H A Dkwbimage.cfg77 # bit0: 0, OpenPage enabled
95 # bit0: 0, DDR DLL enabled
123 # bit0: 1, Window enabled
148 #bit0=1, enable DDR init upon this register write
/rk3399_rockchip-uboot/board/Marvell/openrd/
H A Dkwbimage.cfg77 # bit0: 0, OpenPage enabled
95 # bit0: 0, DDR DLL enabled
123 # bit0: 1, Window enabled
149 #bit0=1, enable DDR init upon this register write
/rk3399_rockchip-uboot/board/iomega/iconnect/
H A Dkwbimage.cfg77 # bit0: 0, OpenPage enabled
95 # bit0: 0, DDR DLL enabled
123 # bit0: 0x1, Window enabled
148 # bit0: 0x1, enable DDR init upon this register write
/rk3399_rockchip-uboot/board/d-link/dns325/
H A Dkwbimage.cfg87 # bit0: 0, OPEn=OpenPage enabled
105 # bit0: 0, DRAM DLL enabled
145 # bit0: 1, Window enabled
153 # bit0: 1, Window enabled
188 # bit0: 1, enable DDR init upon this register write
/rk3399_rockchip-uboot/board/buffalo/lsxl/
H A Dkwbimage-lschl.cfg93 # bit0: 0, OPEn=OpenPage enabled
114 # bit0: 0, DRAM DLL enabled
161 # bit0: 1, Window enabled
209 # bit0: 1, enable DDR init upon this register write
H A Dkwbimage-lsxhl.cfg93 # bit0: 0, OPEn=OpenPage enabled
114 # bit0: 0, DRAM DLL enabled
161 # bit0: 1, Window enabled
209 # bit0: 1, enable DDR init upon this register write
/rk3399_rockchip-uboot/arch/arm/dts/
H A Darmada-xp-synology-ds414.dts313 syno_id_bit0_pin: syno-id-bit0-pin {