Searched refs:bandwidth (Results 1 – 11 of 11) sorted by relevance
308 u64 bandwidth; in rk618_dsi_set_hs_clk() local310 bandwidth = (u64)mode->clock * 1000 * bpp; in rk618_dsi_set_hs_clk()311 do_div(bandwidth, lanes); in rk618_dsi_set_hs_clk()314 bandwidth *= 10; in rk618_dsi_set_hs_clk()315 do_div(bandwidth, 9); in rk618_dsi_set_hs_clk()317 do_div(bandwidth, USEC_PER_SEC); in rk618_dsi_set_hs_clk()318 bandwidth *= USEC_PER_SEC; in rk618_dsi_set_hs_clk()319 fout = bandwidth; in rk618_dsi_set_hs_clk()
635 u8 *bandwidth) in analogix_dp_get_max_rx_bandwidth() argument654 *bandwidth = drm_dp_link_rate_to_bw_code(max_link_rate); in analogix_dp_get_max_rx_bandwidth()666 *bandwidth = data; in analogix_dp_get_max_rx_bandwidth()
6 * bandwidth.
6 optimized to support the high-bandwidth DDR3L memory and
6 high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports.
22 with prioritization and bandwidth allocation amongst CoreNet endpoints23 - 150 Gbps coherent read bandwidth106 prioritization and bandwidth allocation
18 NULL packets, according to input bandwidth of RGB interface.
22 with prioritization and bandwidth allocation amongst CoreNet endpoints23 - 150 Gbps coherent read bandwidth
30 non-coherent out of order transactions with prioritization and bandwidth43 bandwidth saving and high utilization of processor elements. The 9856-Kbyte
5 optimized to support the high-bandwidth DDR3 memory ports, as well as the