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Searched refs:asserted (Results 1 – 25 of 25) sorted by relevance

/rk3399_rockchip-uboot/drivers/reset/
H A Dsandbox-reset.c16 bool asserted; member
46 sbr->signals[reset_ctl->id].asserted = true; in sandbox_reset_assert()
57 sbr->signals[reset_ctl->id].asserted = false; in sandbox_reset_deassert()
107 return sbr->signals[id].asserted; in sandbox_reset_query()
/rk3399_rockchip-uboot/board/Marvell/openrd/
H A Dkwbimage.cfg136 # bit3-0: 0010, (read) M_ODT[0] is asserted during read from DRAM CS1
137 # bit7-4: 0001, (read) M_ODT[1] is asserted during read from DRAM CS0
138 # bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1.
139 # bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0.
143 # bit3-0: 1111, internal ODT is asserted during read from DRAM bank 0-3
/rk3399_rockchip-uboot/board/buffalo/lsxl/
H A Dkwbimage-lschl.cfg181 # bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM
182 # bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM
184 # bit19-16: 0b1100, (write) M_ODT[0] is asserted during write to DRAM CS2, CS3
185 # bit23-20: 0b0011, (write) M_ODT[1] is asserted during write to DRAM CS0, CS1
196 # bit3-0: 0b1111, internal ODT is asserted during read from DRAM bank 0-3
197 # bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-3
H A Dkwbimage-lsxhl.cfg181 # bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM
182 # bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM
184 # bit19-16: 0b0001, (write) M_ODT[0] is asserted during write to DRAM CS0
185 # bit23-20: 0b0000, (write) M_ODT[1] is not asserted during write to DRAM
196 # bit3-0: 0b1111, internal ODT is asserted during read from DRAM bank 0-3
197 # bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-3
/rk3399_rockchip-uboot/board/d-link/dns325/
H A Dkwbimage.cfg163 # bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM
164 # bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM
166 # bit19-16: 0b0011, (write) M_ODT[0] is asserted during write to DRAM CS0 and CS1
167 # bit23-20: 0b0000, (write) M_ODT[1] is not asserted during write to DRAM
176 # bit3-0: 0b0011, internal ODT is asserted during read from DRAM bank 0-1
177 # bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-4
/rk3399_rockchip-uboot/board/LaCie/netspace_v2/
H A Dkwbimage.cfg134 # bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
135 # bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
143 # bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
144 # bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
H A Dkwbimage-is2.cfg134 # bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
135 # bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
143 # bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
144 # bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
H A Dkwbimage-ns2l.cfg134 # bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
135 # bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
143 # bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
144 # bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
/rk3399_rockchip-uboot/board/cloudengines/pogo_e02/
H A Dkwbimage.cfg140 # bit3-0: 2, ODT0Rd, MODT[0] asserted during read from DRAM CS1
141 # bit7-4: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
142 # bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
143 # bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
/rk3399_rockchip-uboot/board/raidsonic/ib62x0/
H A Dkwbimage.cfg137 # bit3-0: ODT0Rd, MODT[0] asserted during read from DRAM CS1
138 # bit7-4: ODT0Rd, MODT[0] asserted during read from DRAM CS0
139 # bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
140 # bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
/rk3399_rockchip-uboot/board/keymile/km_arm/
H A Dkwbimage.cfg145 # bit3-0: 0, ODT0Rd, MODT[0] asserted during read from DRAM CS0
146 # bit19-16:0, ODT0Wr, MODT[0] asserted during write to DRAM CS0
154 # bit3-0: F, ODT0Rd, Internal ODT asserted during read from DRAM bank0
155 # bit7-4: 0, ODT0Wr, Internal ODT asserted during write to DRAM bank0
H A Dkwbimage_128M16_1.cfg229 # bit 3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0
230 # bit 7-4: 0, ODT0Rd, MODT[1] not asserted
233 # bit 19-16: 1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
234 # bit 23-20: 0, ODT0Wr, MODT[1] not asserted
244 # bit 3-0: 1, ODTRd, Internal ODT asserted during read from DRAM bank0
245 # bit 7-4: 0, ODTWr, Internal ODT not asserted during write to DRAM
H A Dkwbimage_256M8_1.cfg231 # bit 3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0
232 # bit 7-4: 0, ODT0Rd, MODT[1] not asserted
235 # bit 19-16: 1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
236 # bit 23-20: 0, ODT0Wr, MODT[1] not asserted
246 # bit 3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
247 # bit 7-4: 0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0
H A Dkwbimage-memphis.cfg160 # bit3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0
161 # bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
169 # bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
170 # bit7-4: 0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0
/rk3399_rockchip-uboot/board/LaCie/net2big_v2/
H A Dkwbimage.cfg134 # bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
135 # bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
143 # bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
144 # bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
/rk3399_rockchip-uboot/board/iomega/iconnect/
H A Dkwbimage.cfg136 # bit3-0: ODT0Rd, MODT[0] asserted during read from DRAM CS1
137 # bit7-4: ODT0Rd, MODT[0] asserted during read from DRAM CS0
138 # bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
139 # bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
/rk3399_rockchip-uboot/doc/device-tree-bindings/spi/
H A Dspi-cadence.txt20 are de-asserted between transactions.
/rk3399_rockchip-uboot/board/Synology/ds109/
H A Dopenocd.cfg29 # re-examine the target again here when nSRST is asserted which
/rk3399_rockchip-uboot/doc/
H A DREADME.i2c39 3. Checks EC_CLAIM. If this is not asserted, then the AP has the bus, and we
/rk3399_rockchip-uboot/doc/device-tree-bindings/reset/
H A Dreset.txt75 child device has reset asserted.
/rk3399_rockchip-uboot/doc/device-tree-bindings/gpio/
H A Dgpio.txt76 GPIO controller that achieves (or represents, for inputs) a logically asserted
77 value at the device. The exact definition of logically asserted should be
/rk3399_rockchip-uboot/arch/arm/dts/
H A Drk3399-puma.dtsi107 * reset signal asserted). Even though it is an enable signal, we
/rk3399_rockchip-uboot/lib/libxbc/
H A DCOPYING174 incurred by, or claims asserted against, such Contributor by reason
/rk3399_rockchip-uboot/test/py/
H A DREADME.md13 It is asserted that writing test-related code in Python is simpler and more
/rk3399_rockchip-uboot/
H A DREADME2144 after PROB_B has been de-asserted during a Virtex II