Searched refs:_no (Results 1 – 4 of 4) sorted by relevance
| /rk3399_rockchip-uboot/drivers/clk/rockchip/ |
| H A D | clk_rk3066.c | 95 #define PLL_DIVISORS(hz, _nr, _no) {\ argument
96 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
97 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
98 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
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| H A D | clk_rk3188.c | 93 #define PLL_DIVISORS(hz, _nr, _no) {\ argument
94 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
95 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
96 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
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| H A D | clk_rk3368.c | 39 #define RK3368_PLL_RATE(_rate, _nr, _nf, _no, _nb) \ argument
44 .no = _no, \
106 #define PLL_DIVISORS(hz, _nr, _no) { \ argument
107 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no}; \
108 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
109 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL " \
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| H A D | clk_rk3288.c | 42 #define RK3288_PLL_RATE(_rate, _nr, _nf, _no, _nb) \ argument
47 .no = _no, \
212 #define PLL_DIVISORS(hz, _nr, _no) {\ argument
213 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
214 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
215 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
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