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Searched refs:V0PLL (Results 1 – 4 of 4) sorted by relevance

/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rk3588.c56 [V0PLL] = PLL(pll_rk3588, PLL_V0PLL, RK3588_PLL_CON(88),
1097 parent = rockchip_pll_get_rate(&rk3588_pll_clks[V0PLL], in rk3588_dclk_vop_get_clk()
1098 priv->cru, V0PLL); in rk3588_dclk_vop_get_clk()
1158 pll_rate = rockchip_pll_get_rate(&rk3588_pll_clks[V0PLL], in rk3588_dclk_vop_set_clk()
1159 priv->cru, V0PLL); in rk3588_dclk_vop_set_clk()
1174 rockchip_pll_set_rate(&rk3588_pll_clks[V0PLL], in rk3588_dclk_vop_set_clk()
1175 priv->cru, V0PLL, div * rate); in rk3588_dclk_vop_set_clk()
1580 rate = rockchip_pll_get_rate(&rk3588_pll_clks[V0PLL], priv->cru, in rk3588_clk_get_rate()
1581 V0PLL); in rk3588_clk_get_rate()
1727 ret = rockchip_pll_set_rate(&rk3588_pll_clks[V0PLL], priv->cru, in rk3588_clk_set_rate()
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H A Dclk_rk3506.c69 [V0PLL] = PLL(pll_rk3328, PLL_V0PLL, RK3506_PLL_CON(8),
1190 priv->v0pll_hz = rockchip_pll_get_rate(&rk3506_pll_clks[V0PLL], in rk3506_clk_init()
1191 priv->cru, V0PLL); in rk3506_clk_init()
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3506.h20 V0PLL, enumerator
H A Dcru_rk3588.h29 V0PLL, enumerator