clk/rockchip/clk_rk3588.c

56 	[V0PLL] = PLL(pll_rk3588, PLL_V0PLL, RK3588_PLL_CON(88),
1097 		parent = rockchip_pll_get_rate(&rk3588_pll_clks[V0PLL],  in rk3588_dclk_vop_get_clk()
1098 					       priv->cru, V0PLL);  in rk3588_dclk_vop_get_clk()
1158 		pll_rate = rockchip_pll_get_rate(&rk3588_pll_clks[V0PLL],  in rk3588_dclk_vop_set_clk()
1159 						 priv->cru, V0PLL);  in rk3588_dclk_vop_set_clk()
1174 			rockchip_pll_set_rate(&rk3588_pll_clks[V0PLL],  in rk3588_dclk_vop_set_clk()
1175 					      priv->cru, V0PLL, div * rate);  in rk3588_dclk_vop_set_clk()
1580 		rate = rockchip_pll_get_rate(&rk3588_pll_clks[V0PLL], priv->cru,  in rk3588_clk_get_rate()
1581 					     V0PLL);  in rk3588_clk_get_rate()
1727 		ret = rockchip_pll_set_rate(&rk3588_pll_clks[V0PLL], priv->cru,  in rk3588_clk_set_rate()
1728 					    V0PLL, rate);  in rk3588_clk_set_rate()
1729 		priv->v0pll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[V0PLL],  in rk3588_clk_set_rate()
1730 						       priv->cru, V0PLL);  in rk3588_clk_set_rate()