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Searched refs:TX (Results 1 – 25 of 26) sorted by relevance

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/rk3399_rockchip-uboot/doc/device-tree-bindings/net/
H A Dmicrel-ksz90x1.txt22 - txen-skew-ps : Skew control of TX CTL pad
27 - txd0-skew-ps : Skew control of TX data 0 pad
28 - txd1-skew-ps : Skew control of TX data 1 pad
29 - txd2-skew-ps : Skew control of TX data 2 pad
30 - txd3-skew-ps : Skew control of TX data 3 pad
108 - txc-skew-ps : Skew control of TX clock pad
113 - txen-skew-ps : Skew control of TX CTL pad
118 - txd0-skew-ps : Skew control of TX data 0 pad
119 - txd1-skew-ps : Skew control of TX data 1 pad
120 - txd2-skew-ps : Skew control of TX data 2 pad
[all …]
H A Dsnps,dwc-qos-ethernet.txt26 In some configurations (e.g. GMII/RGMII), this clock also drives the PHY TX
28 drive the PHY TX path.
116 - snps,txpbl: DMA Programmable burst length for the TX DMA
118 - snps,en-tx-lpi-clockgating: Enable gating of the MAC TX clock during
119 TX low-power mode.
/rk3399_rockchip-uboot/arch/arm/dts/
H A Darmada-8040-mcbin.dts90 * [40,41] CP0 UART1 TX/RX
96 * [51] 2.5G SFP TX fault
209 * [10] CP1 10G SFP TX Disable
216 * [24] CP1 2.5G SFP TX Disable
217 * [26] CP0 10G SFP TX Fault
220 * [29] CP0 10G SFP TX Disable
H A Dsama5d3_can.dtsi21 …AT91_PIOD 15 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS…
29 AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B TX, conflicts with GCOL */
H A Dmeson-gxbb-odroidc2.dts176 gpio-line-names = "UART TX", "UART RX", "VCCK En", "TF 3V3/1V8 En",
187 "Eth RX D3", "Eth RGMII TX Clk", "Eth TX En",
188 "Eth TX D0", "Eth TX D1", "Eth TX D2", "Eth TX D3",
H A Domap3.dtsi490 <59>, /* TX interrupt */
509 <62>, /* TX interrupt */
529 <89>, /* TX interrupt */
548 <54>, /* TX interrupt */
566 <81>, /* TX interrupt */
H A Dtegra30-apalis.dts52 /* PCIE1_RX/TX left disabled */
H A Dsun9i-a80-cx-a99.dts364 * 1 = GND (pointed to by small triangle), 2 = GND, 3 = 3.3 V, 4 = RX, 5 = TX.
H A Dam57xx-beagle-x15-common.dtsi575 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
H A Ddra72-evm-common.dtsi532 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
H A Dmeson-gx.dtsi491 /* HDMI-TX output port */
H A Dam335x-evmsk.dts701 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
H A Dam335x-evm.dts591 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
H A Dam43x-epos-evm.dts796 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
H A Ddra7-evm.dts920 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
H A Dsun6i-a31.dtsi430 * The actual TX clock rate is not controlled by the
H A Dsama5d4.dtsi1510 AT91_PIOE 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* TWCK1, conflicts with UART0 TX and DIBN */
H A Dsun7i-a20.dtsi737 * The actual TX clock rate is not controlled by the
/rk3399_rockchip-uboot/drivers/usb/eth/
H A DKconfig29 Supports 10Base-T/ 100Base-TX/1000Base-T.
38 Supports 10Base-T/ 100Base-TX/1000Base-T.
/rk3399_rockchip-uboot/doc/device-tree-bindings/firmware/
H A Dnvidia,tegra186-bpmp.txt17 - shmem : List of the phandle of the TX and RX shared memory area that
62 The shared memory area for the IPC TX and RX between CPU and BPMP are
/rk3399_rockchip-uboot/drivers/usb/musb/
H A Dmusb_udc.c91 TX, enumerator
358 SET_EP0_STATE(TX); in musb_peri_ep0_tx_data_request()
622 if (TX == ep0_state) in musb_peri_ep0()
/rk3399_rockchip-uboot/drivers/net/
H A Dmacb.c257 #define TX 0 macro
315 macb_flush_ring_desc(macb, TX); in _macb_send()
326 macb_invalidate_ring_desc(macb, TX); in _macb_send()
645 macb_flush_ring_desc(macb, TX); in _macb_init()
/rk3399_rockchip-uboot/drivers/usb/host/
H A DKconfig220 with Intel PCI chipsets (like intel 430TX, 440FX, 440LX, 440BX,
/rk3399_rockchip-uboot/drivers/video/drm/
H A DKconfig173 Rockchip rk3288 SoC has LVDS TX Controller can be used, and it
/rk3399_rockchip-uboot/drivers/video/
H A DKconfig641 Enables the common driver code for the Designware HDMI TX

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