xref: /rk3399_rockchip-uboot/arch/arm/dts/tegra30-apalis.dts (revision 336aee50cf55d4d98ddf3a4412c18286e7f0a4c0)
1bf78b271SMarcel Ziswiler/dts-v1/;
2bf78b271SMarcel Ziswiler
3bf78b271SMarcel Ziswiler#include "tegra30.dtsi"
4bf78b271SMarcel Ziswiler
5bf78b271SMarcel Ziswiler/ {
6bf78b271SMarcel Ziswiler	model = "Toradex Apalis T30";
7bf78b271SMarcel Ziswiler	compatible = "toradex,apalis_t30", "nvidia,tegra30";
8bf78b271SMarcel Ziswiler
99aafef4fSMarcel Ziswiler	chosen {
109aafef4fSMarcel Ziswiler		stdout-path = &uarta;
119aafef4fSMarcel Ziswiler	};
129aafef4fSMarcel Ziswiler
13bf78b271SMarcel Ziswiler	aliases {
14bf78b271SMarcel Ziswiler		i2c0 = "/i2c@7000d000";
15bf78b271SMarcel Ziswiler		i2c1 = "/i2c@7000c000";
16bf78b271SMarcel Ziswiler		i2c2 = "/i2c@7000c500";
17bf78b271SMarcel Ziswiler		i2c3 = "/i2c@7000c700";
1867748a73SStephen Warren		mmc0 = "/sdhci@78000600";
1967748a73SStephen Warren		mmc1 = "/sdhci@78000400";
2067748a73SStephen Warren		mmc2 = "/sdhci@78000000";
21cbaeceabSMarcel Ziswiler		spi0 = "/spi@7000d400";
22cbaeceabSMarcel Ziswiler		spi1 = "/spi@7000dc00";
23cbaeceabSMarcel Ziswiler		spi2 = "/spi@7000de00";
24cbaeceabSMarcel Ziswiler		spi3 = "/spi@7000da00";
25bf78b271SMarcel Ziswiler		usb0 = "/usb@7d000000";
26bf78b271SMarcel Ziswiler		usb1 = "/usb@7d004000";
27bf78b271SMarcel Ziswiler		usb2 = "/usb@7d008000";
28bf78b271SMarcel Ziswiler	};
29bf78b271SMarcel Ziswiler
30bf78b271SMarcel Ziswiler	memory {
31bf78b271SMarcel Ziswiler		device_type = "memory";
32bf78b271SMarcel Ziswiler		reg = <0x80000000 0x40000000>;
33bf78b271SMarcel Ziswiler	};
34bf78b271SMarcel Ziswiler
35bf78b271SMarcel Ziswiler	pcie-controller@00003000 {
36bf78b271SMarcel Ziswiler		status = "okay";
37bf78b271SMarcel Ziswiler		avdd-pexa-supply = <&vdd2_reg>;
38bf78b271SMarcel Ziswiler		vdd-pexa-supply = <&vdd2_reg>;
39bf78b271SMarcel Ziswiler		avdd-pexb-supply = <&vdd2_reg>;
40bf78b271SMarcel Ziswiler		vdd-pexb-supply = <&vdd2_reg>;
41bf78b271SMarcel Ziswiler		avdd-pex-pll-supply = <&vdd2_reg>;
42bf78b271SMarcel Ziswiler		avdd-plle-supply = <&ldo6_reg>;
43bf78b271SMarcel Ziswiler		vddio-pex-ctl-supply = <&sys_3v3_reg>;
44bf78b271SMarcel Ziswiler		hvdd-pex-supply = <&sys_3v3_reg>;
45bf78b271SMarcel Ziswiler
46bf78b271SMarcel Ziswiler		pci@1,0 {
47f0adaf95SMarcel Ziswiler			/* TS_DIFF1/2/3/4 left disabled */
48bf78b271SMarcel Ziswiler			nvidia,num-lanes = <4>;
49bf78b271SMarcel Ziswiler		};
50bf78b271SMarcel Ziswiler
51bf78b271SMarcel Ziswiler		pci@2,0 {
52f0adaf95SMarcel Ziswiler			/* PCIE1_RX/TX left disabled */
53bf78b271SMarcel Ziswiler			nvidia,num-lanes = <1>;
54bf78b271SMarcel Ziswiler		};
55bf78b271SMarcel Ziswiler
56bf78b271SMarcel Ziswiler		pci@3,0 {
57bf78b271SMarcel Ziswiler			status = "okay";
58bf78b271SMarcel Ziswiler			nvidia,num-lanes = <1>;
59bf78b271SMarcel Ziswiler		};
60bf78b271SMarcel Ziswiler	};
61bf78b271SMarcel Ziswiler
62bf78b271SMarcel Ziswiler	/*
63bf78b271SMarcel Ziswiler	 * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier
64bf78b271SMarcel Ziswiler	 * board)
65bf78b271SMarcel Ziswiler	 */
66bf78b271SMarcel Ziswiler	i2c@7000c000 {
67bf78b271SMarcel Ziswiler		status = "okay";
68*33848eb5SMarcel Ziswiler		clock-frequency = <400000>;
69bf78b271SMarcel Ziswiler	};
70bf78b271SMarcel Ziswiler
71bf78b271SMarcel Ziswiler	/* GEN2_I2C: unused */
72bf78b271SMarcel Ziswiler
73bf78b271SMarcel Ziswiler	/*
74bf78b271SMarcel Ziswiler	 * CAM_I2C: I2C3_SDA/SCL on MXM3 pin 201/203 (e.g. camera sensor on
75bf78b271SMarcel Ziswiler	 * carrier board)
76bf78b271SMarcel Ziswiler	 */
77bf78b271SMarcel Ziswiler	i2c@7000c500 {
78bf78b271SMarcel Ziswiler		status = "okay";
79*33848eb5SMarcel Ziswiler		clock-frequency = <400000>;
80bf78b271SMarcel Ziswiler	};
81bf78b271SMarcel Ziswiler
82bf78b271SMarcel Ziswiler	/* DDC: I2C2_SDA/SCL on MXM3 pin 205/207 (e.g. display EDID) */
83bf78b271SMarcel Ziswiler	i2c@7000c700 {
84bf78b271SMarcel Ziswiler		status = "okay";
85*33848eb5SMarcel Ziswiler		clock-frequency = <10000>;
86bf78b271SMarcel Ziswiler	};
87bf78b271SMarcel Ziswiler
88bf78b271SMarcel Ziswiler	/*
89bf78b271SMarcel Ziswiler	 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
90bf78b271SMarcel Ziswiler	 * touch screen controller
91bf78b271SMarcel Ziswiler	 */
92bf78b271SMarcel Ziswiler	i2c@7000d000 {
93bf78b271SMarcel Ziswiler		status = "okay";
94bf78b271SMarcel Ziswiler		clock-frequency = <100000>;
95bf78b271SMarcel Ziswiler
96bf78b271SMarcel Ziswiler		pmic: tps65911@2d {
97bf78b271SMarcel Ziswiler			compatible = "ti,tps65911";
98bf78b271SMarcel Ziswiler			reg = <0x2d>;
99bf78b271SMarcel Ziswiler
100bf78b271SMarcel Ziswiler			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
101bf78b271SMarcel Ziswiler			#interrupt-cells = <2>;
102bf78b271SMarcel Ziswiler			interrupt-controller;
103bf78b271SMarcel Ziswiler
104bf78b271SMarcel Ziswiler			ti,system-power-controller;
105bf78b271SMarcel Ziswiler
106bf78b271SMarcel Ziswiler			#gpio-cells = <2>;
107bf78b271SMarcel Ziswiler			gpio-controller;
108bf78b271SMarcel Ziswiler
109bf78b271SMarcel Ziswiler			vcc1-supply = <&sys_3v3_reg>;
110bf78b271SMarcel Ziswiler			vcc2-supply = <&sys_3v3_reg>;
111bf78b271SMarcel Ziswiler			vcc3-supply = <&vio_reg>;
112bf78b271SMarcel Ziswiler			vcc4-supply = <&sys_3v3_reg>;
113bf78b271SMarcel Ziswiler			vcc5-supply = <&sys_3v3_reg>;
114bf78b271SMarcel Ziswiler			vcc6-supply = <&vio_reg>;
115bf78b271SMarcel Ziswiler			vcc7-supply = <&charge_pump_5v0_reg>;
116bf78b271SMarcel Ziswiler			vccio-supply = <&sys_3v3_reg>;
117bf78b271SMarcel Ziswiler
118bf78b271SMarcel Ziswiler			regulators {
119bf78b271SMarcel Ziswiler				#address-cells = <1>;
120bf78b271SMarcel Ziswiler				#size-cells = <0>;
121bf78b271SMarcel Ziswiler
122bf78b271SMarcel Ziswiler				/* SW1: +V1.35_VDDIO_DDR */
123bf78b271SMarcel Ziswiler				vdd1_reg: vdd1 {
124bf78b271SMarcel Ziswiler					regulator-name = "vddio_ddr_1v35";
125bf78b271SMarcel Ziswiler					regulator-min-microvolt = <1350000>;
126bf78b271SMarcel Ziswiler					regulator-max-microvolt = <1350000>;
127bf78b271SMarcel Ziswiler					regulator-always-on;
128bf78b271SMarcel Ziswiler				};
129bf78b271SMarcel Ziswiler
130bf78b271SMarcel Ziswiler				/* SW2: +V1.05 */
131bf78b271SMarcel Ziswiler				vdd2_reg: vdd2 {
132bf78b271SMarcel Ziswiler					regulator-name =
133bf78b271SMarcel Ziswiler						"vdd_pexa,vdd_pexb,vdd_sata";
134bf78b271SMarcel Ziswiler					regulator-min-microvolt = <1050000>;
135bf78b271SMarcel Ziswiler					regulator-max-microvolt = <1050000>;
136bf78b271SMarcel Ziswiler				};
137bf78b271SMarcel Ziswiler
138bf78b271SMarcel Ziswiler				/* SW CTRL: +V1.0_VDD_CPU */
139bf78b271SMarcel Ziswiler				vddctrl_reg: vddctrl {
140bf78b271SMarcel Ziswiler					regulator-name = "vdd_cpu,vdd_sys";
141bf78b271SMarcel Ziswiler					regulator-min-microvolt = <1150000>;
142bf78b271SMarcel Ziswiler					regulator-max-microvolt = <1150000>;
143bf78b271SMarcel Ziswiler					regulator-always-on;
144bf78b271SMarcel Ziswiler				};
145bf78b271SMarcel Ziswiler
146bf78b271SMarcel Ziswiler				/* SWIO: +V1.8 */
147bf78b271SMarcel Ziswiler				vio_reg: vio {
148bf78b271SMarcel Ziswiler					regulator-name = "vdd_1v8_gen";
149bf78b271SMarcel Ziswiler					regulator-min-microvolt = <1800000>;
150bf78b271SMarcel Ziswiler					regulator-max-microvolt = <1800000>;
151bf78b271SMarcel Ziswiler					regulator-always-on;
152bf78b271SMarcel Ziswiler				};
153bf78b271SMarcel Ziswiler
154bf78b271SMarcel Ziswiler				/* LDO1: unused */
155bf78b271SMarcel Ziswiler
156bf78b271SMarcel Ziswiler				/*
157bf78b271SMarcel Ziswiler				 * EN_+V3.3 switching via FET:
158bf78b271SMarcel Ziswiler				 * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN
159bf78b271SMarcel Ziswiler				 * see also v3_3 fixed supply
160bf78b271SMarcel Ziswiler				 */
161bf78b271SMarcel Ziswiler				ldo2_reg: ldo2 {
162bf78b271SMarcel Ziswiler					regulator-name = "en_3v3";
163bf78b271SMarcel Ziswiler					regulator-min-microvolt = <3300000>;
164bf78b271SMarcel Ziswiler					regulator-max-microvolt = <3300000>;
165bf78b271SMarcel Ziswiler					regulator-always-on;
166bf78b271SMarcel Ziswiler				};
167bf78b271SMarcel Ziswiler
168bf78b271SMarcel Ziswiler				/* +V1.2_CSI */
169bf78b271SMarcel Ziswiler				ldo3_reg: ldo3 {
170bf78b271SMarcel Ziswiler					regulator-name =
171bf78b271SMarcel Ziswiler						"avdd_dsi_csi,pwrdet_mipi";
172bf78b271SMarcel Ziswiler					regulator-min-microvolt = <1200000>;
173bf78b271SMarcel Ziswiler					regulator-max-microvolt = <1200000>;
174bf78b271SMarcel Ziswiler				};
175bf78b271SMarcel Ziswiler
176bf78b271SMarcel Ziswiler				/* +V1.2_VDD_RTC */
177bf78b271SMarcel Ziswiler				ldo4_reg: ldo4 {
178bf78b271SMarcel Ziswiler					regulator-name = "vdd_rtc";
179bf78b271SMarcel Ziswiler					regulator-min-microvolt = <1200000>;
180bf78b271SMarcel Ziswiler					regulator-max-microvolt = <1200000>;
181bf78b271SMarcel Ziswiler					regulator-always-on;
182bf78b271SMarcel Ziswiler				};
183bf78b271SMarcel Ziswiler
184bf78b271SMarcel Ziswiler				/*
185bf78b271SMarcel Ziswiler				 * +V2.8_AVDD_VDAC:
186bf78b271SMarcel Ziswiler				 * only required for analog RGB
187bf78b271SMarcel Ziswiler				 */
188bf78b271SMarcel Ziswiler				ldo5_reg: ldo5 {
189bf78b271SMarcel Ziswiler					regulator-name = "avdd_vdac";
190bf78b271SMarcel Ziswiler					regulator-min-microvolt = <2800000>;
191bf78b271SMarcel Ziswiler					regulator-max-microvolt = <2800000>;
192bf78b271SMarcel Ziswiler					regulator-always-on;
193bf78b271SMarcel Ziswiler				};
194bf78b271SMarcel Ziswiler
195bf78b271SMarcel Ziswiler				/*
196bf78b271SMarcel Ziswiler				 * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V
197bf78b271SMarcel Ziswiler				 * but LDO6 can't set voltage in 50mV
198bf78b271SMarcel Ziswiler				 * granularity
199bf78b271SMarcel Ziswiler				 */
200bf78b271SMarcel Ziswiler				ldo6_reg: ldo6 {
201bf78b271SMarcel Ziswiler					regulator-name = "avdd_plle";
202bf78b271SMarcel Ziswiler					regulator-min-microvolt = <1100000>;
203bf78b271SMarcel Ziswiler					regulator-max-microvolt = <1100000>;
204bf78b271SMarcel Ziswiler				};
205bf78b271SMarcel Ziswiler
206bf78b271SMarcel Ziswiler				/* +V1.2_AVDD_PLL */
207bf78b271SMarcel Ziswiler				ldo7_reg: ldo7 {
208bf78b271SMarcel Ziswiler					regulator-name = "avdd_pll";
209bf78b271SMarcel Ziswiler					regulator-min-microvolt = <1200000>;
210bf78b271SMarcel Ziswiler					regulator-max-microvolt = <1200000>;
211bf78b271SMarcel Ziswiler					regulator-always-on;
212bf78b271SMarcel Ziswiler				};
213bf78b271SMarcel Ziswiler
214bf78b271SMarcel Ziswiler				/* +V1.0_VDD_DDR_HS */
215bf78b271SMarcel Ziswiler				ldo8_reg: ldo8 {
216bf78b271SMarcel Ziswiler					regulator-name = "vdd_ddr_hs";
217bf78b271SMarcel Ziswiler					regulator-min-microvolt = <1000000>;
218bf78b271SMarcel Ziswiler					regulator-max-microvolt = <1000000>;
219bf78b271SMarcel Ziswiler					regulator-always-on;
220bf78b271SMarcel Ziswiler				};
221bf78b271SMarcel Ziswiler			};
222bf78b271SMarcel Ziswiler		};
223bf78b271SMarcel Ziswiler	};
224bf78b271SMarcel Ziswiler
225bf78b271SMarcel Ziswiler	/* SPI1: Apalis SPI1 */
226bf78b271SMarcel Ziswiler	spi@7000d400 {
227bf78b271SMarcel Ziswiler		status = "okay";
228bf78b271SMarcel Ziswiler		spi-max-frequency = <25000000>;
229bf78b271SMarcel Ziswiler	};
230bf78b271SMarcel Ziswiler
231bf78b271SMarcel Ziswiler	/* SPI4: CAN2 */
232bf78b271SMarcel Ziswiler	spi@7000da00 {
233bf78b271SMarcel Ziswiler		status = "okay";
234bf78b271SMarcel Ziswiler		spi-max-frequency = <25000000>;
235bf78b271SMarcel Ziswiler	};
236bf78b271SMarcel Ziswiler
237bf78b271SMarcel Ziswiler	/* SPI5: Apalis SPI2 */
238bf78b271SMarcel Ziswiler	spi@7000dc00 {
239bf78b271SMarcel Ziswiler		status = "okay";
240bf78b271SMarcel Ziswiler		spi-max-frequency = <25000000>;
241bf78b271SMarcel Ziswiler	};
242bf78b271SMarcel Ziswiler
243bf78b271SMarcel Ziswiler	/* SPI6: CAN1 */
244bf78b271SMarcel Ziswiler	spi@7000de00 {
245bf78b271SMarcel Ziswiler		status = "okay";
246bf78b271SMarcel Ziswiler		spi-max-frequency = <25000000>;
247bf78b271SMarcel Ziswiler	};
248bf78b271SMarcel Ziswiler
249bf78b271SMarcel Ziswiler	sdhci@78000000 {
250bf78b271SMarcel Ziswiler		status = "okay";
251bf78b271SMarcel Ziswiler		bus-width = <4>;
25272731118SMarcel Ziswiler		/* SD1_CD# */
25372731118SMarcel Ziswiler		cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_LOW>;
254bf78b271SMarcel Ziswiler	};
255bf78b271SMarcel Ziswiler
256bf78b271SMarcel Ziswiler	sdhci@78000400 {
257bf78b271SMarcel Ziswiler		status = "okay";
258bf78b271SMarcel Ziswiler		bus-width = <8>;
25972731118SMarcel Ziswiler		/* MMC1_CD# */
26072731118SMarcel Ziswiler		cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
261bf78b271SMarcel Ziswiler	};
262bf78b271SMarcel Ziswiler
263bf78b271SMarcel Ziswiler	sdhci@78000600 {
264bf78b271SMarcel Ziswiler		status = "okay";
265bf78b271SMarcel Ziswiler		bus-width = <8>;
266bf78b271SMarcel Ziswiler		non-removable;
267bf78b271SMarcel Ziswiler	};
268bf78b271SMarcel Ziswiler
269bf78b271SMarcel Ziswiler	/* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */
270bf78b271SMarcel Ziswiler	usb@7d000000 {
271bf78b271SMarcel Ziswiler		status = "okay";
27229ce9995SMarcel Ziswiler		dr_mode = "otg";
27372731118SMarcel Ziswiler		/* USBO1_EN */
2742b2b50bcSSimon Glass		nvidia,vbus-gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
275bf78b271SMarcel Ziswiler	};
276bf78b271SMarcel Ziswiler
277bf78b271SMarcel Ziswiler	/* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */
278bf78b271SMarcel Ziswiler	usb@7d004000 {
279bf78b271SMarcel Ziswiler		status = "okay";
28072731118SMarcel Ziswiler		/* USBH_EN */
2812b2b50bcSSimon Glass		nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
282bf78b271SMarcel Ziswiler	};
283bf78b271SMarcel Ziswiler
284bf78b271SMarcel Ziswiler	/* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */
285bf78b271SMarcel Ziswiler	usb@7d008000 {
286bf78b271SMarcel Ziswiler		status = "okay";
28772731118SMarcel Ziswiler		/* USBH_EN */
2882b2b50bcSSimon Glass		nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
289bf78b271SMarcel Ziswiler	};
290bf78b271SMarcel Ziswiler
291ce2f2d2aSStephen Warren	clocks {
292ce2f2d2aSStephen Warren		compatible = "simple-bus";
293ce2f2d2aSStephen Warren		#address-cells = <1>;
294ce2f2d2aSStephen Warren		#size-cells = <0>;
295ce2f2d2aSStephen Warren
296ce2f2d2aSStephen Warren		clk32k_in: clk@0 {
297ce2f2d2aSStephen Warren			compatible = "fixed-clock";
298ce2f2d2aSStephen Warren			reg=<0>;
299ce2f2d2aSStephen Warren			#clock-cells = <0>;
300ce2f2d2aSStephen Warren			clock-frequency = <32768>;
301ce2f2d2aSStephen Warren		};
302ce2f2d2aSStephen Warren		clk16m: clk@1 {
303ce2f2d2aSStephen Warren			compatible = "fixed-clock";
304ce2f2d2aSStephen Warren			reg=<1>;
305ce2f2d2aSStephen Warren			#clock-cells = <0>;
306ce2f2d2aSStephen Warren			clock-frequency = <16000000>;
307ce2f2d2aSStephen Warren			clock-output-names = "clk16m";
308ce2f2d2aSStephen Warren		};
309ce2f2d2aSStephen Warren	};
310ce2f2d2aSStephen Warren
311bf78b271SMarcel Ziswiler	regulators {
312bf78b271SMarcel Ziswiler		compatible = "simple-bus";
313bf78b271SMarcel Ziswiler		#address-cells = <1>;
314bf78b271SMarcel Ziswiler		#size-cells = <0>;
315bf78b271SMarcel Ziswiler
316bf78b271SMarcel Ziswiler		sys_3v3_reg: regulator@100 {
317bf78b271SMarcel Ziswiler			compatible = "regulator-fixed";
318bf78b271SMarcel Ziswiler			reg = <100>;
319bf78b271SMarcel Ziswiler			regulator-name = "3v3";
320bf78b271SMarcel Ziswiler			regulator-min-microvolt = <3300000>;
321bf78b271SMarcel Ziswiler			regulator-max-microvolt = <3300000>;
322bf78b271SMarcel Ziswiler			regulator-always-on;
323bf78b271SMarcel Ziswiler		};
324bf78b271SMarcel Ziswiler
325bf78b271SMarcel Ziswiler		charge_pump_5v0_reg: regulator@101 {
326bf78b271SMarcel Ziswiler			compatible = "regulator-fixed";
327bf78b271SMarcel Ziswiler			reg = <101>;
328bf78b271SMarcel Ziswiler			regulator-name = "5v0";
329bf78b271SMarcel Ziswiler			regulator-min-microvolt = <5000000>;
330bf78b271SMarcel Ziswiler			regulator-max-microvolt = <5000000>;
331bf78b271SMarcel Ziswiler			regulator-always-on;
332bf78b271SMarcel Ziswiler		};
333bf78b271SMarcel Ziswiler	};
334bf78b271SMarcel Ziswiler};
335f53dcc0eSSimon Glass
336f53dcc0eSSimon Glass&uarta {
337f53dcc0eSSimon Glass	status = "okay";
338f53dcc0eSSimon Glass};
339