Searched refs:RL (Results 1 – 9 of 9) sorted by relevance
| /rk3399_rockchip-uboot/drivers/ddr/microchip/ |
| H A D | ddr2.c | 39 writel(SCL_BURST8 | SCL_DDR_CONNECTED | SCL_RCAS_LAT(RL) | in ddr2_phy_init()
169 ((RL - WL + 3) << 28)), &ctrl->dlycfg0); in ddr2_ctrl_init()
178 (((RL + 5) >> 4) << 29) | in ddr2_ctrl_init()
187 ((RL + 3) << 28)), &ctrl->dlycfg2); in ddr2_ctrl_init()
197 writel(ODTRDLY(RL - 3) | ODTWDLY(WL - 3) | ODTRLEN(2) | ODTWLEN(3), in ddr2_ctrl_init()
229 host_load_cmd(ctrl, 5, temp, LOAD_MODE_CMD | (RL << 28) | (2 << 24), in ddr2_ctrl_init()
242 host_load_cmd(ctrl, 9, temp, LOAD_MODE_CMD | (RL << 28) | (3 << 24), in ddr2_ctrl_init()
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| H A D | ddr2_timing.h | 18 #define RL 5 macro
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| /rk3399_rockchip-uboot/arch/arm/mach-omap2/omap4/ |
| H A D | emif.c | 26 .RL = 6,
50 .RL = 3,
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| H A D | sdram_elpida.c | 193 .RL = 6,
216 .RL = 5,
239 .RL = 3,
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| /rk3399_rockchip-uboot/arch/arm/mach-omap2/omap5/ |
| H A D | emif.c | 27 .RL = 8,
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| H A D | sdram.c | 611 .RL = 8,
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| /rk3399_rockchip-uboot/arch/arm/mach-omap2/ |
| H A D | emif-common.c | 555 u8 RL) in get_sdram_config_reg() argument
565 config_reg |= RL << EMIF_REG_CL_SHIFT; in get_sdram_config_reg()
754 static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL) in get_ddr_phy_ctrl_1() argument
758 phy |= (RL + 2) << EMIF_REG_READ_LATENCY_SHIFT; in get_ddr_phy_ctrl_1()
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-mx5/ |
| H A D | imx-regs.h | 181 #define RL(x) (((x) & 0x3) << 8) macro
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| /rk3399_rockchip-uboot/arch/arm/include/asm/ |
| H A D | emif.h | 1096 u8 RL; member
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