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Searched refs:PINMUX_CFG_REG (Results 1 – 10 of 10) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/mach-rmobile/
H A Dpfc-r8a7791.c439 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
473 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
507 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
541 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
575 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
609 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
643 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
677 { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) {
984 { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } },
985 { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
[all …]
H A Dpfc-r8a7792.c880 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
914 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
948 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
982 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
1016 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
1050 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
1084 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
1118 { PINMUX_CFG_REG("GPSR7", 0xE6060020, 32, 1) {
1152 { PINMUX_CFG_REG("GPSR8", 0xE6060024, 32, 1) {
1186 { PINMUX_CFG_REG("GPSR9", 0xE6060028, 32, 1) {
[all …]
H A Dpfc-r8a7793.c1039 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
1073 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
1107 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
1141 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
1175 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
1209 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
1243 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
1277 { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) {
1793 { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } },
1794 { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
[all …]
H A Dpfc-r8a7794.c866 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
900 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
934 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
968 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
1002 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
1036 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
1070 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
1478 { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } },
1479 { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
1513 { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { GP_INOUTSEL(2) } },
[all …]
H A Dpfc-r8a7795.c3339 { PINMUX_CFG_REG("GPSR0", 0xE6060100, 32, 1) {
3378 { PINMUX_CFG_REG("GPSR1", 0xE6060104, 32, 1) {
3415 { PINMUX_CFG_REG("GPSR2", 0xE6060108, 32, 1) {
3453 { PINMUX_CFG_REG("GPSR3", 0xE606010C, 32, 1) {
3490 { PINMUX_CFG_REG("GPSR4", 0xE6060110, 32, 1) {
3527 { PINMUX_CFG_REG("GPSR5", 0xE6060114, 32, 1) {
3562 { PINMUX_CFG_REG("GPSR6", 0xE6060118, 32, 1) {
3597 { PINMUX_CFG_REG("GPSR7", 0xE606011C, 32, 1) {
4646 { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) {
4683 { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
[all …]
H A Dpfc-r8a7796.c3516 { PINMUX_CFG_REG("GPSR0", 0xE6060100, 32, 1) {
3555 { PINMUX_CFG_REG("GPSR1", 0xE6060104, 32, 1) {
3592 { PINMUX_CFG_REG("GPSR2", 0xE6060108, 32, 1) {
3630 { PINMUX_CFG_REG("GPSR3", 0xE606010C, 32, 1) {
3667 { PINMUX_CFG_REG("GPSR4", 0xE6060110, 32, 1) {
3704 { PINMUX_CFG_REG("GPSR5", 0xE6060114, 32, 1) {
3740 { PINMUX_CFG_REG("GPSR6", 0xE6060118, 32, 1) {
3775 { PINMUX_CFG_REG("GPSR7", 0xE606011C, 32, 1) {
4895 { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) {
4932 { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
[all …]
H A Dpfc-r8a7790.c1125 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
1159 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
1193 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
1227 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
1261 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
1295 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
1685 { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } },
1686 { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
1720 { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) {
1754 { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } },
[all …]
H A Dpfc-r8a7740.c2341 { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
2368 { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) {
2381 { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) {
2400 { PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1) {
H A Dpfc-sh73a0.c2523 { PINMUX_CFG_REG("MSEL2CR", 0xe605801c, 32, 1) {
2558 { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) {
2593 { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) {
/rk3399_rockchip-uboot/include/
H A Dsh_pfc.h51 #define PINMUX_CFG_REG(name, r, r_width, f_width) \ macro
186 PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \