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Searched refs:M2 (Results 1 – 22 of 22) sorted by relevance

/rk3399_rockchip-uboot/board/ti/am57xx/
H A Dmux_data.h16 {GPMC_AD0, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad0.vin3a_d0 */
17 {GPMC_AD1, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad1.vin3a_d1 */
18 {GPMC_AD2, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad2.vin3a_d2 */
19 {GPMC_AD3, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad3.vin3a_d3 */
20 {GPMC_AD4, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad4.vin3a_d4 */
21 {GPMC_AD5, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad5.vin3a_d5 */
22 {GPMC_AD6, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad6.vin3a_d6 */
23 {GPMC_AD7, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad7.vin3a_d7 */
24 {GPMC_AD8, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad8.vin3a_d8 */
25 {GPMC_AD9, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad9.vin3a_d9 */
[all …]
/rk3399_rockchip-uboot/board/compulab/cm_t54/
H A Dmux.c43 {I2C5_SCL, (PTU | IEN | M2)}, /* UART4_RX */
44 {I2C5_SDA, (M2)}, /* UART4_TX */
/rk3399_rockchip-uboot/board/overo/
H A Dovero.h107 MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTU | EN | M2)) /*MMC3_CLK*/\
108 MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /*MMC3_CMD*/\
110 MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT3*/\
111 MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT0*/\
112 MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT1*/\
113 MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT2*/\
/rk3399_rockchip-uboot/arch/xtensa/include/asm/arch-de212/
H A Dtie-asm.h79 rsr.M2 \at1 // MAC16 option
134 wsr.M2 \at1 // MAC16 option
/rk3399_rockchip-uboot/arch/xtensa/include/asm/arch-dc232b/
H A Dtie-asm.h52 rsr \at1, M2
95 wsr \at1, M2
/rk3399_rockchip-uboot/arch/xtensa/include/asm/arch-dc233c/
H A Dtie-asm.h88 rsr \at1, M2 // MAC16 option
153 wsr \at1, M2 // MAC16 option
/rk3399_rockchip-uboot/board/lg/sniper/
H A Dsniper.h96 MUX_VAL(CP(GPMC_WAIT2), (IDIS | PTD | DIS | M2)) /* gpio_64 */ \
97 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTD | DIS | M2)) /* gpio_65 */ \
133 MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M2)) /* csi2_dx2 */ \
134 MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M2)) /* csi2_dy2 */ \
275 MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTD | DIS | M2)) /* sdmmc3_clk */ \
276 MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /* sdmmc3_cmd */ \
280 MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M2)) /* sdmmc3_dat3 */ \
281 MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M2)) /* sdmmc3_dat0 */ \
282 MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M2)) /* sdmmc3_dat1 */ \
283 MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M2)) /* sdmmc3_dat2 */ \
/rk3399_rockchip-uboot/board/freescale/bsc9132qds/
H A DREADME48 - 512 KB, 8-way, level 2 unified instruction/data cache (L2 cache/M2 memory)
110 0xB000_0000 0xB0FF_FFFF DSP core0 M2 space 16M
111 0xB100_0000 0xB1FF_FFFF DSP core1 M2 space 16M
/rk3399_rockchip-uboot/board/pandora/
H A Dpandora.h175 MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTD | DIS | M2)) /*MMC3_CLK*/\
176 MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /*MMC3_CMD*/\
177 MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT0*/\
178 MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT1*/\
179 MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT2*/\
180 MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT3*/\
/rk3399_rockchip-uboot/board/freescale/bsc9131rdb/
H A DREADME56 . 512 Kbyte 8-way level 2 unified instruction/data cache (M2 memory)
104 0xA0000000 0xBFFFFFFF Shared DSP core L2/M2 space 512M
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-omap5/
H A Dmux_omap5.h42 #define M2 2 macro
H A Dmux_dra7xx.h46 #define M2 2 macro
/rk3399_rockchip-uboot/board/sunxi/
H A DMAINTAINERS124 BANANAPI M2 ULTRA BOARD
130 BANANAPI M2 MAGIC BOARD
346 SINOVOIP BPI M2 PLUS H3 BOARD
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-omap4/
H A Dmux_omap4.h50 #define M2 2 macro
/rk3399_rockchip-uboot/arch/arm/dts/
H A Dsun8i-r40-bananapi-m2-ultra.dts47 model = "Banana Pi BPI-M2-Ultra";
H A Dsun6i-a31s-sinovoip-bpi-m2.dts49 model = "Sinovoip BPI-M2";
H A Dsun8i-h3-bananapi-m2-plus.dts52 model = "Banana Pi BPI-M2-Plus";
/rk3399_rockchip-uboot/board/teejet/mt_ventoux/
H A Dmt_ventoux.h233 MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M2)) \
235 MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M2)) \
237 MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M2)) \
239 MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M2)) \
/rk3399_rockchip-uboot/board/htkw/mcx/
H A Dmcx.h278 MUX_VAL(CP(CCDC_FIELD), (IDIS | PTD | DIS | M2)) \
280 MUX_VAL(CP(CCDC_HD), (IDIS | PTD | DIS | M2)) \
282 MUX_VAL(CP(CCDC_VD), (IEN | PTD | EN | M2)) \
284 MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M2)) \
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-omap3/
H A Dmux.h44 #define M2 2 macro
/rk3399_rockchip-uboot/board/technexion/twister/
H A Dtwister.h120 MUX_VAL(CP(GPMC_NCS2), (IDIS | PTD | EN | M2)) /*PWM9*/\
/rk3399_rockchip-uboot/
H A DREADME383 This value denotes start offset of M2 memory