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Searched refs:L2 (Results 1 – 25 of 64) sorted by relevance

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/rk3399_rockchip-uboot/board/freescale/bsc9131rdb/
H A DREADME10 L2 cache
11 . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
48 . 256-Kbyte L2 cache/L2 memory/L2 stash
104 0xA0000000 0xBFFFFFFF Shared DSP core L2/M2 space 512M
/rk3399_rockchip-uboot/doc/
H A DREADME.mpc74xx10 There is a framework in place to enable the L2 cache, and to program
12 sets up the L2 cache, so it's not enabled. (IMHO, it shouldn't be
H A DREADME.boston56 - L2 cache support
H A DREADME.t1040-l2switch1 This file contains information for VSC9953, a Vitesse L2 Switch IP
/rk3399_rockchip-uboot/arch/arm/dts/
H A Dimx6q.dtsi29 next-level-cache = <&L2>;
63 next-level-cache = <&L2>;
70 next-level-cache = <&L2>;
77 next-level-cache = <&L2>;
H A Dimx6dl.dtsi28 next-level-cache = <&L2>;
58 next-level-cache = <&L2>;
H A Drk3188.dtsi24 next-level-cache = <&L2>;
43 next-level-cache = <&L2>;
49 next-level-cache = <&L2>;
55 next-level-cache = <&L2>;
H A Dsocfpga.dtsi36 next-level-cache = <&L2>;
42 next-level-cache = <&L2>;
616 L2: l2-cache@fffef000 { label
H A Dsocfpga_arria10.dtsi53 next-level-cache = <&L2>;
59 next-level-cache = <&L2>;
626 L2: l2-cache@fffff000 { label
/rk3399_rockchip-uboot/board/freescale/bsc9132qds/
H A DREADME16 512-Kbyte shared L2 cache
17 - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2
48 - 512 KB, 8-way, level 2 unified instruction/data cache (L2 cache/M2 memory)
109 0xA000_0000 0xA7FF_FFFF DSP core1 L2 space 128M
/rk3399_rockchip-uboot/configs/
H A Dportl2_defconfig4 CONFIG_IDENT_STRING="\nKeymile Port-L2"
/rk3399_rockchip-uboot/Documentation/devicetree/bindings/rtc/
H A Dbrcm,brcmstb-waketimer.txt10 - interrupt-parent: The phandle to the Always-On (AON) Power Management (PM) L2
/rk3399_rockchip-uboot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.soc13 processor cores with datapath acceleration optimized for L2/3 packet
19 - 1 MB unified L2 Cache
97 ECC protected L2 cache.
137 processor cores with datapath acceleration optimized for L2/3 packet
143 - 2 MB unified L2 Cache
227 d) No L2 switch
/rk3399_rockchip-uboot/arch/arm/mach-uniphier/
H A DKconfig79 bool "Enable the UniPhier L2 cache controller"
84 This option allows to use the UniPhier System Cache as L2 cache.
/rk3399_rockchip-uboot/board/freescale/ls1021aqds/
H A DREADME23 protection on both L1 and L2 caches. The LS1021A processor is pin- and
31 - 512 Kbyte shared coherent L2 Cache (with ECC protection)
/rk3399_rockchip-uboot/board/freescale/ls1021atwr/
H A DREADME23 protection on both L1 and L2 caches. The LS1021A processor is pin- and
31 - 512 Kbyte shared coherent L2 Cache (with ECC protection)
/rk3399_rockchip-uboot/board/raidsonic/ib62x0/
H A Dkwbimage.cfg151 DATA 0xffd20134 0x66666666 # L2 RAM Timing 0 Register
152 DATA 0xffd20138 0x66666666 # L2 RAM Timing 1 Register
/rk3399_rockchip-uboot/board/keymile/km_arm/
H A Dkwbimage.cfg37 DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
38 DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
H A Dkwbimage-memphis.cfg40 DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
41 DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
H A Dkwbimage_128M16_1.cfg62 DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
79 DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
H A Dkwbimage_256M8_1.cfg64 DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
81 DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
/rk3399_rockchip-uboot/board/buffalo/lsxl/
H A Dkwbimage-lschl.cfg20 # L2 RAM Timing 0
24 # L2 RAM Timing 1
H A Dkwbimage-lsxhl.cfg20 # L2 RAM Timing 0
24 # L2 RAM Timing 1
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/
H A Dstart.S248 @ lines allocate in the L1 or L2 cache.
301 orr r0, r0, #(0x1 << 27) @ L2 PLD data forwarding disable
/rk3399_rockchip-uboot/board/freescale/t104xrdb/
H A DREADME9 personality of T1040 SoC without Integrated 8-port Gigabit(L2 Switch).
45 - Four e5500 cores, each with a private 256 KB L2 cache

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