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Searched refs:HW (Results 1 – 25 of 35) sorted by relevance

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/rk3399_rockchip-uboot/board/toradex/apalis_imx6/
H A DKconfig43 bool "Apalis iMX6 V1.0 HW"
45 Apalis iMX6 V1.0 HW has a different pinout for the UART.
49 option the config block stating V1.0 HW selects DCE mode,
/rk3399_rockchip-uboot/doc/device-tree-bindings/reset/
H A Dreset.txt21 in hardware for a reset signal to affect multiple logically separate HW blocks
23 the DT node of each affected HW block, since if activated, an unrelated block
26 children of the bus are affected by the reset signal, or an individual HW
28 appropriate software access to the reset signals in order to manage the HW,
29 rather than to slavishly enumerate the reset signal that affects each HW
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/bcm281xx/
H A Dclk-core.h98 #define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW)
181 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
193 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
204 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
223 .flags = FLAG(GATE, HW)|FLAG(GATE, EXISTS), \
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/bcm235xx/
H A Dclk-core.h98 #define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW)
181 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
193 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
204 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
223 .flags = FLAG(GATE, HW)|FLAG(GATE, EXISTS), \
/rk3399_rockchip-uboot/doc/device-tree-bindings/gpio/
H A Dnvidia,tegra186-gpio.txt11 package balls is under the control of a separate pin controller HW block. Two
30 Tegra HW documentation describes a unified naming convention for all GPIOs
44 matches the HW documentation. The values chosen for the names are alphabetically
46 IDs and HW register offsets using a lookup table.
51 of the number of ports it implements. Note that the HW documentation refers to
52 both the overall controller HW module and the sets-of-ports as "controllers".
89 The interrupt outputs from the HW block, one per set of ports, in the
90 order the HW manual describes them. The number of entries required varies
/rk3399_rockchip-uboot/doc/device-tree-bindings/net/
H A Dsnps,dwc-qos-ethernet.txt6 entries in properties are marked as optional, or only required in specific HW
25 The EQOS transmit path clock. The HW signal name is clk_tx_i.
30 The EQOS receive path clock. The HW signal name is clk_rx_i.
41 APB, AHB, AXI, etc. The HW signal name is hclk_i (AHB) or clk_csr_i (other
45 separate clock for the master and slave bus interfaces. The HW signal name
48 The PTP reference clock. The HW signal name is clk_ptp_ref_i.
91 - "eqos". The reset to the entire module. The HW signal name is hreset_n
/rk3399_rockchip-uboot/drivers/mailbox/
H A DKconfig9 CPU to another CPU, or sometimes to dedicated HW modules. They form
/rk3399_rockchip-uboot/doc/
H A DREADME.omap375 To make U-Boot for OMAP3 support NAND device SW or HW ECC calculation, U-Boot
84 enables SW ECC calculation. HW ECC enabled with
89 executed by OMAP3's boot rom and therefore has to be written with HW ECC.
H A DREADME.N121315 - 3 HW-level nested interruptions.
H A DREADME.nokia_rx5122 output with ANSI espace codes and the N900 HW keyboard input. USB tty works
49 * run vgacon - Use framebuffer and HW keyboard for control (default)
H A DREADME.esbc_validate12 SHA-256 and RSA operations are performed using SEC block in HW.
H A DREADME.hwconfig46 enabling HW feature X we may need to disable Y, and turn Z
/rk3399_rockchip-uboot/drivers/power/domain/
H A DKconfig24 simply accepts requests to power on/off various HW modules without
/rk3399_rockchip-uboot/doc/device-tree-bindings/i2c/
H A Dnvidia,tegra186-bpmp-i2c.txt3 In Tegra186, the BPMP (Boot and Power Management Processor) owns certain HW
/rk3399_rockchip-uboot/board/Arcturus/ucp1020/
H A DREADME26 HW Addresses.
/rk3399_rockchip-uboot/drivers/led/
H A DKconfig17 LED HW controller accessed via MMIO registers.
18 HW blinking is supported and up to 24 LEDs can be controlled.
28 LED HW controller accessed via MMIO registers.
29 HW has no blinking capabilities and up to 32 LEDs can be controlled.
/rk3399_rockchip-uboot/board/imgtec/xilfpga/
H A DREADME37 DDR initialization is already handled by a HW IP block.
/rk3399_rockchip-uboot/board/buffalo/lsxl/
H A Dkwbimage-lschl.cfg22 # not further specified in HW manual, timing taken from original vendor port
26 # not further specified in HW manual, timing taken from original vendor port
H A Dkwbimage-lsxhl.cfg22 # not further specified in HW manual, timing taken from original vendor port
26 # not further specified in HW manual, timing taken from original vendor port
/rk3399_rockchip-uboot/drivers/clk/
H A DKconfig39 clocks on BCM6345 SoCs. HW has no rate changing capabilities.
/rk3399_rockchip-uboot/doc/device-tree-bindings/clock/
H A Dnvidia,tegra20-car.txt6 The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
/rk3399_rockchip-uboot/board/freescale/mpc837xemds/
H A DREADME5 For some reason, the HW designers describe the switch settings
/rk3399_rockchip-uboot/board/freescale/mpc832xemds/
H A DREADME5 For some reason, the HW designers describe the switch settings
/rk3399_rockchip-uboot/drivers/reset/
H A DKconfig32 simply accepts requests to reset various HW modules without actually
/rk3399_rockchip-uboot/board/ccv/xpress/
H A Dimximage.cfg98 periodic HW ZQ calibration. */

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