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Searched refs:HIWORD_UPDATE (Results 1 – 13 of 13) sorted by relevance

/rk3399_rockchip-uboot/drivers/video/drm/
H A Drk618.h15 #define HIWORD_UPDATE(v, h, l) (((v) << (l)) | (GENMASK(h, l) << 16)) macro
18 #define FRC_DEN_INV HIWORD_UPDATE(1, 6, 6)
19 #define FRC_SYNC_INV HIWORD_UPDATE(1, 5, 5)
20 #define FRC_DCLK_INV HIWORD_UPDATE(1, 4, 4)
21 #define FRC_OUT_ZERO HIWORD_UPDATE(1, 3, 3)
22 #define FRC_OUT_MODE_RGB666 HIWORD_UPDATE(1, 2, 2)
23 #define FRC_OUT_MODE_RGB888 HIWORD_UPDATE(0, 2, 2)
24 #define FRC_DITHER_MODE_HI_FRC HIWORD_UPDATE(1, 1, 1)
25 #define FRC_DITHER_MODE_FRC HIWORD_UPDATE(0, 1, 1)
26 #define FRC_DITHER_ENABLE HIWORD_UPDATE(1, 0, 0)
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H A Drockchip_lvds.c26 #define HIWORD_UPDATE(v, h, l) (((v) << (l)) | (GENMASK(h, l) << 16)) macro
29 #define PX30_LVDS_SELECT(x) HIWORD_UPDATE(x, 14, 13)
30 #define PX30_LVDS_MODE_EN(x) HIWORD_UPDATE(x, 12, 12)
31 #define PX30_LVDS_MSBSEL(x) HIWORD_UPDATE(x, 11, 11)
32 #define PX30_LVDS_P2S_EN(x) HIWORD_UPDATE(x, 6, 6)
33 #define PX30_LVDS_VOP_SEL(x) HIWORD_UPDATE(x, 1, 1)
36 #define RK3126_LVDS_P2S_EN(x) HIWORD_UPDATE(x, 9, 9)
37 #define RK3126_LVDS_MODE_EN(x) HIWORD_UPDATE(x, 6, 6)
38 #define RK3126_LVDS_MSBSEL(x) HIWORD_UPDATE(x, 3, 3)
39 #define RK3126_LVDS_SELECT(x) HIWORD_UPDATE(x, 2, 1)
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H A Drockchip_dw_hdmi_qp.c28 #define HIWORD_UPDATE(val, mask) ((val) | (mask) << 16) macro
1271 val = HIWORD_UPDATE(0, RK3576_HDMITX_FRL_MOD); in rk3576_set_link_mode()
1273 val = HIWORD_UPDATE(RK3576_HDMITX_FRL_MOD, RK3576_HDMITX_FRL_MOD); in rk3576_set_link_mode()
1288 val = HIWORD_UPDATE(0, RK3588_HDMI21_MASK); in rk3588_set_link_mode()
1294 val = HIWORD_UPDATE(0, RK3588_COMPRESS_MODE_MASK | RK3588_COLOR_FORMAT_MASK); in rk3588_set_link_mode()
1303 val = HIWORD_UPDATE(RK3588_HDMI21_MASK, RK3588_HDMI21_MASK); in rk3588_set_link_mode()
1310 val = HIWORD_UPDATE(RK3588_COMPRESS_MODE_MASK | RK3588_COMPRESSED_DATA, in rk3588_set_link_mode()
1317 val = HIWORD_UPDATE(0, RK3588_COMPRESS_MODE_MASK | RK3588_COLOR_FORMAT_MASK); in rk3588_set_link_mode()
1333 val = HIWORD_UPDATE(0, RK3576_COLOR_FORMAT_MASK); in rk3576_set_color_format()
1337 val = HIWORD_UPDATE(RK3576_YUV420, RK3576_COLOR_FORMAT_MASK); in rk3576_set_color_format()
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H A Drockchip_rgb.c25 #define HIWORD_UPDATE(v, l, h) (((v) << (l)) | (GENMASK(h, l) << 16)) macro
28 #define PX30_RGB_DATA_SYNC_BYPASS(v) HIWORD_UPDATE(v, 3, 3)
29 #define PX30_RGB_VOP_SEL(v) HIWORD_UPDATE(v, 2, 2)
32 #define RK1808_RGB_DATA_SYNC_BYPASS(v) HIWORD_UPDATE(v, 3, 3)
35 #define RV1106_IO_BYPASS_SEL(v) HIWORD_UPDATE(v, 0, 1)
37 #define RV1106_VOP_PIPE_BYPASS(v) HIWORD_UPDATE(v, 0, 1)
40 #define RV1126_LCDC_IO_BYPASS(v) HIWORD_UPDATE(v, 0, 0)
43 #define RV1126B_VOP_MCU_SEL(v) HIWORD_UPDATE(v, 15, 15)
46 #define RK3288_LVDS_LCDC_SEL(v) HIWORD_UPDATE(v, 3, 3)
48 #define RK3288_LVDS_PWRDWN(v) HIWORD_UPDATE(v, 15, 15)
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H A Dsamsung_mipi_dcphy.c29 #define HIWORD_UPDATE(v, h, l) (((v) << (l)) | (GENMASK((h), (l)) << 16)) macro
160 #define S_CPHY_MODE HIWORD_UPDATE(1, 3, 3)
161 #define M_CPHY_MODE HIWORD_UPDATE(1, 0, 0)
/rk3399_rockchip-uboot/drivers/video/drm/rk628/
H A Drk628_cru.h17 #define PLL_BYPASS(x) HIWORD_UPDATE(x, 15, 15)
20 #define PLL_POSTDIV1(x) HIWORD_UPDATE(x, 14, 12)
23 #define PLL_FBDIV(x) HIWORD_UPDATE(x, 11, 0)
27 #define PLL_PD(x) HIWORD_UPDATE(x, 13, 13)
29 #define PLL_DSMPD(x) HIWORD_UPDATE(x, 12, 12)
33 #define PLL_POSTDIV2(x) HIWORD_UPDATE(x, 8, 6)
36 #define PLL_REFDIV(x) HIWORD_UPDATE(x, 5, 0)
82 #define CLK_BT1120DEC_DIV(x) HIWORD_UPDATE(x, 4, 0)
86 #define CLK_HDMIRX_AUD_DIV(x) HIWORD_UPDATE(x, 13, 6)
88 #define CLK_HDMIRX_AUD_SEL(x) HIWORD_UPDATE(x, 15, 14)
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H A Drk628.h25 #define HIWORD_UPDATE(v, h, l) ((((v) << (l)) & GENMASK((h), (l))) | \ macro
69 #define SCL_8_PIXEL_ALIGN(x) HIWORD_UPDATE(x, 12, 12)
70 #define SCL_COLOR_VER_EN(x) HIWORD_UPDATE(x, 10, 10)
71 #define SCL_COLOR_BAR_EN(x) HIWORD_UPDATE(x, 9, 9)
72 #define SCL_VER_DOWN_MODE(x) HIWORD_UPDATE(x, 8, 8)
73 #define SCL_HOR_DOWN_MODE(x) HIWORD_UPDATE(x, 7, 7)
74 #define SCL_BIC_COE_SEL(x) HIWORD_UPDATE(x, 6, 5)
75 #define SCL_VER_MODE(x) HIWORD_UPDATE(x, 4, 3)
76 #define SCL_HOR_MODE(x) HIWORD_UPDATE(x, 2, 1)
77 #define SCL_EN(x) HIWORD_UPDATE(x, 0, 0)
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H A Drk628_hdmirx.c500 rk628_i2c_write(rk628, GRF_GPIO1AB_SEL_CON, HIWORD_UPDATE(0x7, 10, 8)); in rk628_hdmirx_init()
505 rk628_i2c_write(rk628, GRF_GPIO1AB_SEL_CON, HIWORD_UPDATE(0, 0, 0)); in rk628_hdmirx_init()
506 rk628_i2c_write(rk628, GRF_GPIO3AB_SEL_CON, HIWORD_UPDATE(1, 14, 14)); in rk628_hdmirx_init()
H A Drk628_cru.c568 rk628_i2c_write(rk628, CRU_MODE_CON00, HIWORD_UPDATE(1, 4, 4)); in rk628_cru_init()
/rk3399_rockchip-uboot/drivers/pwm/
H A Drk_pwm.c25 #define HIWORD_UPDATE(v, l, h) (((v) << (l)) | (GENMASK(h, l) << 16)) macro
36 #define PWM_CLK_EN(v) HIWORD_UPDATE(v, 0, 0)
37 #define PWM_EN(v) HIWORD_UPDATE(v, 1, 1)
38 #define PWM_CTRL_UPDATE_EN(v) HIWORD_UPDATE(v, 2, 2)
39 #define PWM_GLOBAL_JOIN_EN(v) HIWORD_UPDATE(v, 4, 4)
42 #define CLK_PRESCALE(v) HIWORD_UPDATE(v, 0, 2)
43 #define CLK_SCALE(v) HIWORD_UPDATE(v, 4, 12)
44 #define CLK_SRC_SEL(v) HIWORD_UPDATE(v, 13, 14)
45 #define CLK_GLOBAL_SEL(v) HIWORD_UPDATE(v, 15, 15)
48 #define PWM_MODE(v) HIWORD_UPDATE(v, 0, 1)
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/rk3399_rockchip-uboot/drivers/mmc/
H A Drockchip_dw_mmc.c32 #define HIWORD_UPDATE(val, mask, shift) \ macro
242 dwmci_writel(host, SDMMC_TIMING_CON1, HIWORD_UPDATE(raw_value, 0x07ff, 1)); in rockchip_mmc_set_phase()
244 dwmci_writel(host, SDMMC_TIMING_CON0, HIWORD_UPDATE(raw_value, 0x07ff, 1)); in rockchip_mmc_set_phase()
/rk3399_rockchip-uboot/drivers/net/
H A Dgmac_rockchip.c62 #define HIWORD_UPDATE(val, mask, shift) ((val) << (shift) | (mask) << ((shift) + 16)) macro
66 #define RK3576_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
67 #define RK3576_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
/rk3399_rockchip-uboot/drivers/video/rk_eink/
H A Drk_ebc_tcon.c34 #define HIWORD_UPDATE(x, l, h) (((x) << (l)) | (GENMASK(h, l) << 16)) macro