| /rk3399_rockchip-uboot/arch/arm/mach-rockchip/rv1126/ |
| H A D | rv1126.c | 69 #define CRU_BASE 0xFF490000 macro
617 writel(0x00ff0055, CRU_BASE + CRU_CLKSEL_CON65); in arch_cpu_init()
618 writel(0x00ff0055, CRU_BASE + CRU_CLKSEL_CON67); in arch_cpu_init()
635 writel(0x00ff0003, CRU_BASE + CRU_CLKSEL_CON02); in arch_cpu_init()
636 writel(0x00ff0005, CRU_BASE + CRU_CLKSEL_CON03); in arch_cpu_init()
637 writel(0xffff8383, CRU_BASE + CRU_CLKSEL_CON27); in arch_cpu_init()
638 writel(0x00ff0083, CRU_BASE + CRU_CLKSEL_CON31); in arch_cpu_init()
639 writel(0x00ff0083, CRU_BASE + CRU_CLKSEL_CON33); in arch_cpu_init()
640 writel(0xffff4385, CRU_BASE + CRU_CLKSEL_CON40); in arch_cpu_init()
641 writel(0x00ff0043, CRU_BASE + CRU_CLKSEL_CON49); in arch_cpu_init()
[all …]
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| /rk3399_rockchip-uboot/board/rockchip/evb_rv1106/ |
| H A D | evb_rv1106.c | 14 #define CRU_BASE 0xFF3B2000 macro
36 writel(0x1 << 7 | 0x1 << 23, CRU_BASE + CRU_SOFTRST_CON04); in usb_reset_otg_controller()
38 writel(0x0 << 7 | 0x1 << 23, CRU_BASE + CRU_SOFTRST_CON04); in usb_reset_otg_controller()
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| /rk3399_rockchip-uboot/board/rockchip/evb_rk3528/ |
| H A D | evb_rk3528.c | 17 #define CRU_BASE 0xff4a0000 macro
44 writel(0x00020002, CRU_BASE + CRU_SOFTRST_CON33); in usb_reset_otg_controller()
46 writel(0x00020000, CRU_BASE + CRU_SOFTRST_CON33); in usb_reset_otg_controller()
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| /rk3399_rockchip-uboot/board/rockchip/evb_rk3576/ |
| H A D | evb_rk3576.c | 17 #define CRU_BASE 0x27200000 macro
44 writel(0x00200020, CRU_BASE + CRU_SOFTRST_CON47); in usb_reset_otg_controller()
46 writel(0x00200000, CRU_BASE + CRU_SOFTRST_CON47); in usb_reset_otg_controller()
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| /rk3399_rockchip-uboot/board/rockchip/evb_rk3588/ |
| H A D | evb_rk3588.c | 17 #define CRU_BASE 0xfd7c0000 macro
44 writel(0x00100010, CRU_BASE + CRU_SOFTRST_CON42); in usb_reset_otg_controller()
46 writel(0x00100000, CRU_BASE + CRU_SOFTRST_CON42); in usb_reset_otg_controller()
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| /rk3399_rockchip-uboot/board/rockchip/evb_rk3568/ |
| H A D | evb_rk3568.c | 18 #define CRU_BASE 0xfdd20000 macro
45 writel(0x00100010, CRU_BASE + CRU_SOFTRST_CON09); in usb_reset_otg_controller()
47 writel(0x00100000, CRU_BASE + CRU_SOFTRST_CON09); in usb_reset_otg_controller()
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| /rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3506/ |
| H A D | rk3506.c | 48 #define CRU_BASE 0xff9a0000 macro
159 writel(0x18c0, CRU_BASE + CRU_GLB_RST_CON); in arch_cpu_init()
201 writel(0x0c000000, CRU_BASE + CRU_GATE_CON5); in fit_standalone_release()
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| /rk3399_rockchip-uboot/arch/arm/mach-rockchip/ |
| H A D | spl_pcie_ep_boot.c | 554 #define CRU_BASE 0xFDD20000 macro
555 #define CRU_GATE_CON12 (CRU_BASE + 0x330)
556 #define CRU_GATE_CON13 (CRU_BASE + 0x334)
557 #define CRU_GATE_CON33 (CRU_BASE + 0x384)
558 #define CRU_SOFTRST_CON12 (CRU_BASE + 0x430)
559 #define CRU_SOFTRST_CON27 (CRU_BASE + 0x46c)
571 writel(0x00040004, CRU_BASE + 0x104); in pcie_first_reset()
572 writel(0x00700010, CRU_BASE); in pcie_first_reset()
574 writel(0xFDB9, CRU_BASE + CRU_GLB_SRST_FST_OFFSET); in pcie_first_reset()
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| /rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3328/ |
| H A D | rk3328.c | 17 #define CRU_BASE 0xFF440000 macro
95 writel((3 << (8 + 16)) | (2 << 8), CRU_BASE + 0x148); in board_debug_uart_init()
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| /rk3399_rockchip-uboot/arch/arm/mach-rockchip/rv1106/ |
| H A D | rv1106.c | 102 #define CRU_BASE 0xff3b0000 macro
486 writel(0x85f, CRU_BASE + CRU_GLB_RST_CON); in arch_cpu_init()
496 writel(0xffff0018, CRU_BASE + CRU_PVTPLL0_CON1_L); in arch_cpu_init()
497 writel(0x00030003, CRU_BASE + CRU_PVTPLL0_CON0_L); in arch_cpu_init()
498 writel(0xffff0018, CRU_BASE + CRU_PVTPLL1_CON1_L); in arch_cpu_init()
499 writel(0x00030003, CRU_BASE + CRU_PVTPLL1_CON0_L); in arch_cpu_init()
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| /rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3308/ |
| H A D | rk3308.c | 50 #define CRU_BASE 0xff500000 macro
218 writel(0x80008000, CRU_BASE + CRU_CLKGATE_CON10); in arch_cpu_init()
219 writel(0x88888888, CRU_BASE + CRU_CLKGATE_CON11); in arch_cpu_init()
220 writel(0x88888888, CRU_BASE + CRU_CLKGATE_CON12); in arch_cpu_init()
223 static struct rk3308_cru * const cru = (void *)CRU_BASE; in arch_cpu_init()
306 static struct rk3308_cru * const cru = (void *)CRU_BASE; in board_debug_uart_init()
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| /rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3568/ |
| H A D | rk3568.c | 42 #define CRU_BASE 0xfdd20000 macro
802 writel(0x04000400, CRU_BASE + CRU_SOFTRST_CON26); in fit_standalone_release()
810 writel(0x04000000, CRU_BASE + CRU_SOFTRST_CON26); in fit_standalone_release()
906 writel(0x02a002a0, CRU_BASE + CRU_SOFTRST_CON28); in arch_cpu_init()
978 writel(0x04000400, CRU_BASE + CRU_SOFTRST_CON26); in spl_fit_standalone_release()
984 writel(0x04000000, CRU_BASE + CRU_SOFTRST_CON26); in spl_fit_standalone_release()
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| /rk3399_rockchip-uboot/arch/arm/mach-rockchip/px30/ |
| H A D | px30.c | 59 #define CRU_BASE 0xff2b0000 macro
269 #define CRU_BASE 0xff2b0000 macro
273 static struct px30_cru * const cru = (void *)CRU_BASE; in board_debug_uart_init()
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| /rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3588/ |
| H A D | rk3588.c | 85 #define CRU_BASE 0xfd7c0000 macro
999 writel(0x01c001c0, CRU_BASE + CRU_SOFTRST_CON77); in arch_cpu_init()
1438 writel(0x00f00042, CRU_BASE + CRU_GPLL_CON1); in fit_standalone_release()
1445 writel(0x08400840, CRU_BASE + CRU_GLB_RST_CON); in fit_standalone_release()
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| /rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3036/ |
| H A D | sdram_rk3036.c | 20 #define CRU_BASE 0x20000000 macro
745 sdram_priv.cru = (void *)CRU_BASE; in sdram_init()
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| /rk3399_rockchip-uboot/drivers/ram/rockchip/ |
| H A D | sdram_rk3308.c | 27 #define CRU_BASE 0xff500000 macro
859 sdram_priv.cru = (void *)CRU_BASE; in sdram_init()
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