rockchip: px30: Invoke do_board_download() for px30s

Maskrom download can prevent to flash px30s board with px30
update.img, because px30 ddr.bin can't work on px30s which is
early than download act

rockchip: px30: Invoke do_board_download() for px30s

Maskrom download can prevent to flash px30s board with px30
update.img, because px30 ddr.bin can't work on px30s which is
early than download action.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I7c5673818b1ce14a0ce0ea7e093275a076cccc41

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rockchip: px30: set usb2phy parameter for px30s

Change-Id: I6197e4986455b72d4a92e4fe8e35646912fb53d8
Signed-off-by: Liang Chen <cl@rock-chips.com>

rockchip: px30: fixup regulators for px30s/rk3326s

Assume that all regulators are from RK809/817.

For px30s
1. fixed min/max 1.0v => 0.9v
2. vdd_logic suspend volt: any => 0.85v

For px30
1. Modify

rockchip: px30: fixup regulators for px30s/rk3326s

Assume that all regulators are from RK809/817.

For px30s
1. fixed min/max 1.0v => 0.9v
2. vdd_logic suspend volt: any => 0.85v

For px30
1. Modify regulator-off-in-suspend => regulator-on-in-suspend
in regulator vdd_logic/vcc_3v0/vcc_1v0/vccio_sd/vcc_sd.
2. Modify sleep-mode RKPM_SLP_ARMOFF_LOGOFF => RKPM_SLP_ARMOFF
in rockchip-suspend node.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Idae6efcd53003304fd01923b8162460d3048013d

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rockchip: px30: fixup pcfg drive-strength for px30s

Traversing max depth2 of all nodes from root path "/".

Time-Stat example: cpu on 816Mhz spends about 7ms on
traversing total 272 nodes, including

rockchip: px30: fixup pcfg drive-strength for px30s

Traversing max depth2 of all nodes from root path "/".

Time-Stat example: cpu on 816Mhz spends about 7ms on
traversing total 272 nodes, including fixup some of them.

Change-Id: I9121111f270dc9af97c8ed05cdfdd63dc6e82b4c
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

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rockchip: px30s: set the emmc drive strength

- set the emmc data(GPIO1A0-A7) drive strength to 14.2ma
- set the emmc clock(GPIO1B1) drive strength to 23.7ma
- set the emmc cmd(GPIO1B2) drive strengt

rockchip: px30s: set the emmc drive strength

- set the emmc data(GPIO1A0-A7) drive strength to 14.2ma
- set the emmc clock(GPIO1B1) drive strength to 23.7ma
- set the emmc cmd(GPIO1B2) drive strength to 14.2ma

Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I2ec02d514069f606c4660be85c9d4eefee54b5d8

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rockchip: px30: add dmc fsp support for px30s

Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
Change-Id: I0cf05272ef5debae8436eb4b3765d9219df27b63

rockchip: px30: fixup some fdt nodes for px30s

1. fixup opp table.
2. fixup bus apll.
3. use scmi_clk.
4. fixup i2s soft reset num.

Change-Id: I0fb660ea9066e8ec9b8b8c88228171d98e0d9bfb
Signed-off-b

rockchip: px30: fixup some fdt nodes for px30s

1. fixup opp table.
2. fixup bus apll.
3. use scmi_clk.
4. fixup i2s soft reset num.

Change-Id: I0fb660ea9066e8ec9b8b8c88228171d98e0d9bfb
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

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rockchip: px30: switch VCCIO6 voltage controlled by io_vsel6

According to the description of GRF_IO_VSEL, the voltage of
VCCIO6(which is the concern of emmc/flash/sfc controller) will
indicate by GP

rockchip: px30: switch VCCIO6 voltage controlled by io_vsel6

According to the description of GRF_IO_VSEL, the voltage of
VCCIO6(which is the concern of emmc/flash/sfc controller) will
indicate by GPIO0_B6 or io_vsel6. The SOC defaults use GPIO0_B6
to indicate power supply voltage for VCCIO6 by hardware, then
we can switch to io_vsel6 after system power on, and release
GPIO0_B6 for other usage.

Change-Id: I9c8339e357a7328d9ffeb711ba5d0bdd41971101
Signed-off-by: Liang Chen <cl@rock-chips.com>

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Merge branch 'next-dev' into thunder-boot

rockchip: px30: Enable support for UART5

Because the UART2 IOs are mux with SDcard, in order to use SDCard,
we need to use UART5(on evb RPi connector) instead of UART2M0

Change-Id: Ibeab51636eb748f

rockchip: px30: Enable support for UART5

Because the UART2 IOs are mux with SDcard, in order to use SDCard,
we need to use UART5(on evb RPi connector) instead of UART2M0

Change-Id: Ibeab51636eb748f389d9211193c0b5682c266c9e
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

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rockchip: px30: disable ddr secure region

Disable the ddr secure region so that emmc/sd controller can access
the DRAM, this reg should be override in ATF.

Change-Id: I30ed494bbe0ec93d162cc84a815ab

rockchip: px30: disable ddr secure region

Disable the ddr secure region so that emmc/sd controller can access
the DRAM, this reg should be override in ATF.

Change-Id: I30ed494bbe0ec93d162cc84a815ab591a00eb0e5
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

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rockchip: rk3326: add AArch32 execution state support

Support boot ARMv8 based RK3326 on AARCH32 state

Change-Id: Ifb788ba71057f4f72dba9e1071c3609308644a9b
Signed-off-by: Joseph Chen <chenjh@rock-c

rockchip: rk3326: add AArch32 execution state support

Support boot ARMv8 based RK3326 on AARCH32 state

Change-Id: Ifb788ba71057f4f72dba9e1071c3609308644a9b
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

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clk: rockchip: px30: print arm enter and init rate

Change-Id: I0d2a1c6bb92397210314322fd147c4a8a6e81abd
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

ARCH: arm: px30: clear force_jtag mode

If SDMMC0_DET pull low gpio1_d4/d5 mux as sdmmc functions, otherwise
they mux as JTAG or UART. But the jtag_force(grf_cpu_con1[7])
is enable after reset.

This

ARCH: arm: px30: clear force_jtag mode

If SDMMC0_DET pull low gpio1_d4/d5 mux as sdmmc functions, otherwise
they mux as JTAG or UART. But the jtag_force(grf_cpu_con1[7])
is enable after reset.

This clear force_jtag mode to enable uart4 when SDMMC0_DET is high.

Change-Id: I2a2dadaad7dc2df8de3b43ff47d27d266caca62f
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>

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rockchip: px30: disable video phy bandgap by default to reduce power consumption

Change-Id: I98f84a9fd73a42252c695ab0dcc8fe0185ecd611
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>

rockchip: px30: fix GPIO IOMUX define error

Change-Id: Ic0c9b1d8b4889769a29e918e1c7d5129d5b67290
Signed-off-by: YouMin Chen <cym@rock-chips.com>

rockchip: px30: add setting QOS Priority in TPL

Change-Id: I26cbf7c3cd88c27c81f5bd80657348611857ae8d
Signed-off-by: YouMin Chen <cym@rock-chips.com>

rockchip: px30: enable FIFO for uart in board_debug_uart_init

Change-Id: I87a49f871625e9a705cd1a5e33db162d8c761048
Signed-off-by: YouMin Chen <cym@rock-chips.com>

rockchip: px30: add UART clock and iomux for TPL_BUILD

Change-Id: Id2fed3e99e0e421063e006fcf857fed889216b72
Signed-off-by: YouMin Chen <cym@rock-chips.com>

rockchip: px30: implement set_armclk_rate()

Add support to set armclk rate.

Change-Id: Ie96d8680e9b3666f8131aeb553594a271d426566
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

rockchip: px30: do not switch UART iomux in U-Boot proper

pre-loader should already set the correct UART iomux, but not set the
m0/m1 select;
The UART2 and SD card share the IO in PX30, so we can no

rockchip: px30: do not switch UART iomux in U-Boot proper

pre-loader should already set the correct UART iomux, but not set the
m0/m1 select;
The UART2 and SD card share the IO in PX30, so we can not swith it in
case the SD card is using it and pinctrl does not work properly at
very beginning.

Change-Id: I9c757b6e14dbe671c121b0068db0c21c1b670545
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

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px30: arch_cpu_init: Fix error pd_vo bit

Change-Id: I3b93425732183bc1b627cf489164955818a873fa
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

px30: arch_cpu_init: enable pd_vo

Change-Id: I789b5e759c962604e6bb22922b0e73eb8cfd63a9
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

rockchip: px30: fix grf reg base

fix base addr to correct grf reg base.

Change-Id: I71b1fc8c5ea9ea246290f79b73d3c6055b7ea017
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

rockchip: px30: add new soc support

The Rockchip PX30 is a ARM-based SoC with a quad-core Cortex-A35
including NEON and GPU, Mali-400 graphics, several DDR3 options
and video codec support. Peripher

rockchip: px30: add new soc support

The Rockchip PX30 is a ARM-based SoC with a quad-core Cortex-A35
including NEON and GPU, Mali-400 graphics, several DDR3 options
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.

Change-Id: I0c3c58aa654d42291ae902593285bc974cda19d5
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

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