1 /*
2 * SPDX-License-Identifier: GPL-2.0+
3 *
4 * (C) Copyright 2022 Rockchip Electronics Co., Ltd
5 */
6
7 #include <common.h>
8 #include <asm/io.h>
9 #include <dwc3-uboot.h>
10 #include <usb.h>
11
12 DECLARE_GLOBAL_DATA_PTR;
13
14 #define CRU_BASE 0xFF3B2000
15 #define CRU_SOFTRST_CON04 0x0A10
16
17 #ifdef CONFIG_USB_DWC3
18 static struct dwc3_device dwc3_device_data = {
19 .maximum_speed = USB_SPEED_HIGH,
20 .base = 0xffb00000,
21 .dr_mode = USB_DR_MODE_PERIPHERAL,
22 .index = 0,
23 .dis_u2_susphy_quirk = 1,
24 .usb2_phyif_utmi_width = 16,
25 };
26
usb_gadget_handle_interrupts(void)27 int usb_gadget_handle_interrupts(void)
28 {
29 dwc3_uboot_handle_interrupt(0);
30 return 0;
31 }
32
33 #ifdef CONFIG_SUPPORT_USBPLUG
usb_reset_otg_controller(void)34 static void usb_reset_otg_controller(void)
35 {
36 writel(0x1 << 7 | 0x1 << 23, CRU_BASE + CRU_SOFTRST_CON04);
37 mdelay(1);
38 writel(0x0 << 7 | 0x1 << 23, CRU_BASE + CRU_SOFTRST_CON04);
39
40 mdelay(1);
41 }
42 #endif
43
board_usb_init(int index,enum usb_init_type init)44 int board_usb_init(int index, enum usb_init_type init)
45 {
46 #ifdef CONFIG_SUPPORT_USBPLUG
47 usb_reset_otg_controller();
48 #endif
49 writel(0x01ff0000, 0xff000050); /* Resume usb2 phy to normal mode */
50
51 return dwc3_uboot_init(&dwc3_device_data);
52 }
53 #endif
54