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Searched refs:CLK_PWM1_DIV_MASK (Results 1 – 6 of 6) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3506.h184 CLK_PWM1_DIV_MASK = 0xf << CLK_PWM1_DIV_SHIFT, enumerator
H A Dcru_rv1126.h186 CLK_PWM1_DIV_MASK = 0x7f << CLK_PWM1_DIV_SHIFT, enumerator
H A Dcru_rv1126b.h380 CLK_PWM1_DIV_MASK = 0x3 << CLK_PWM1_DIV_SHIFT, enumerator
/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rk3506.c739 div = (con & CLK_PWM1_DIV_MASK) >> CLK_PWM1_DIV_SHIFT; in rk3506_pwm_get_rate()
782 CLK_PWM1_SEL_MASK | CLK_PWM1_DIV_MASK, in rk3506_pwm_set_rate()
H A Dclk_rv1126.c277 div = (con & CLK_PWM1_DIV_MASK) >> CLK_PWM1_DIV_SHIFT; in rv1126_pwm_get_pmuclk()
319 CLK_PWM1_DIV_MASK, 0); in rv1126_pwm_set_pmuclk()
324 CLK_PWM1_DIV_MASK, in rv1126_pwm_set_pmuclk()
H A Dclk_rv1126b.c603 div = (con & CLK_PWM1_DIV_MASK) >> in rv1126b_pwm_get_clk()
666 CLK_PWM1_DIV_MASK, in rv1126b_pwm_set_clk()