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Searched refs:CL (Results 1 – 25 of 26) sorted by relevance

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/rk3399_rockchip-uboot/arch/arm/mach-sunxi/
H A Ddram_sun9i.c92 u32 CL; member
363 u32 CL = 0; in mctl_channel_init() local
440 CL = para->cl_cwl_table[i].CL; in mctl_channel_init()
443 debug("found CL/CWL: CL = %d, CWL = %d\n", CL, CWL); in mctl_channel_init()
448 if ((CL == 0) && (CWL == 0)) { in mctl_channel_init()
464 DDR3_MR0_CL(CL); in mctl_channel_init()
528 #define RD2WR (CL + MCTL_BL/2 + 2 - CWL) in mctl_channel_init()
542 writel((MCTL_DIV2(CWL) << 24) | (MCTL_DIV2(CL) << 16) | in mctl_channel_init()
576 writel((2 << 24) | ((MCTL_DIV2(CL) - 2) << 16) | in mctl_channel_init()
863 { .CL = 5, .CWL = 5, .tCKmin = 3000, .tCKmax = 3300 }, in sunxi_dram_init()
[all …]
/rk3399_rockchip-uboot/board/Seagate/nas220/
H A Dkwbimage.cfg26 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
41 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
42 # bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
90 # bit6-4: 4, CL=5
/rk3399_rockchip-uboot/board/compulab/cl-som-am57x/
H A DMAINTAINERS1 CL-SOM-AM57x BOARD
/rk3399_rockchip-uboot/board/Marvell/guruplug/
H A Dkwbimage.cfg23 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
38 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
39 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
87 # bit6-4: 4, CL=5
/rk3399_rockchip-uboot/board/Seagate/dockstar/
H A Dkwbimage.cfg26 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
41 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
42 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
90 # bit6-4: 4, CL=5
/rk3399_rockchip-uboot/board/Synology/ds109/
H A Dkwbimage.cfg27 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
42 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
43 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
91 # bit6-4: 4, CL=5
/rk3399_rockchip-uboot/board/Marvell/dreamplug/
H A Dkwbimage.cfg24 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
39 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
40 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
88 # bit6-4: 4, CL=5
/rk3399_rockchip-uboot/board/Seagate/goflexhome/
H A Dkwbimage.cfg29 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
44 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
45 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
93 # bit6-4: 4, CL=5
/rk3399_rockchip-uboot/board/Marvell/sheevaplug/
H A Dkwbimage.cfg23 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
38 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
39 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
87 # bit6-4: 4, CL=5
/rk3399_rockchip-uboot/board/LaCie/netspace_v2/
H A Dkwbimage.cfg24 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
39 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
40 # bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
87 # bit6-4: 4, CL=5
H A Dkwbimage-is2.cfg24 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
39 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
40 # bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
87 # bit6-4: 4, CL=5
H A Dkwbimage-ns2l.cfg24 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
39 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
40 # bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
87 # bit6-4: 4, CL=5
/rk3399_rockchip-uboot/board/cloudengines/pogo_e02/
H A Dkwbimage.cfg27 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
42 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
43 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
91 # bit6-4: 4, CL=5
/rk3399_rockchip-uboot/board/raidsonic/ib62x0/
H A Dkwbimage.cfg24 # Dram initalization for SINGLE x16 CL=5 @ 400MHz
39 # bit23-20: 0x5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
40 # bit27-24: 0x7, CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
88 # bit6-4: 0x4, CL=5
/rk3399_rockchip-uboot/board/LaCie/net2big_v2/
H A Dkwbimage.cfg24 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
39 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
40 # bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
87 # bit6-4: 4, CL=5
/rk3399_rockchip-uboot/board/Marvell/openrd/
H A Dkwbimage.cfg23 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
38 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
39 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
87 # bit6-4: 4, CL=5
/rk3399_rockchip-uboot/board/iomega/iconnect/
H A Dkwbimage.cfg23 # Dram initalization for SINGLE x16 CL=5 @ 400MHz
38 # bit23-20: 0x5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
39 # bit27-24: 0x7, CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
87 # bit6-4: 0x4, CL=5
/rk3399_rockchip-uboot/board/d-link/dns325/
H A Dkwbimage.cfg27 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
48 # bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
49 # bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
97 # bit6-4: 5, CAS Latency (CL) 5
/rk3399_rockchip-uboot/board/buffalo/lsxl/
H A Dkwbimage-lschl.cfg50 # bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
51 # bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
105 # bit6-4: 5, CAS Latency (CL) 5
H A Dkwbimage-lsxhl.cfg50 # bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
51 # bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
105 # bit6-4: 5, CAS Latency (CL) 5
/rk3399_rockchip-uboot/board/keymile/km_arm/
H A Dkwbimage.cfg59 # bit23-20: 3=recommended value for CL=3 and STARTBURST_DEL disabled bit31=0
60 # bit27-24: 6= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
H A Dkwbimage-memphis.cfg62 # bit23-20: 5=recommended value for CL=4 and STARTBURST_DEL disabled bit31=0
63 # bit27-24: 8= CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
H A Dkwbimage_128M16_1.cfg113 # bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0
114 # bit 27-24: 6, CL+1, STARTBURST sample stages, for freqs 200-399MHz, unbuffered DIMM
H A Dkwbimage_256M8_1.cfg115 # bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0
116 # bit 27-24: 6, CL+1, STARTBURST sample stages, freq 200-399MHz, unbuffer DIMM
/rk3399_rockchip-uboot/arch/arm/mach-omap2/omap5/
H A DKconfig13 bool "CompuLab CL-SOM-AM57x"

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