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Searched refs:x5 (Results 1 – 25 of 66) sorted by relevance

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/rk3399_ARM-atf/plat/nxp/common/aarch64/
H A Dbl31_data.S388 ldr x5, =BC_PSCI_BASE
391 str x6, [x5], #8
392 dc cvac, x5
393 str xzr, [x5], #8
394 dc cvac, x5
395 str xzr, [x5], #8
396 dc cvac, x5
397 str xzr, [x5], #8
398 dc cvac, x5
399 str xzr, [x5], #8
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/pmu/
H A Dplat_pmu_macros.S43 lsr x5, x0, #6
44 ldr w3, [x4, x5]
45 str wzr, [x4, x5]
89 mov x5, PMU_BASE
90 ldr w0, [x5, #PMU_SFT_CON]
93 str w0, [x5, #PMU_SFT_CON]
96 ldr w1, [x5, #PMU_DDR_SREF_ST]
110 mov x5, CRU_BASE
113 str w0, [x5, #CRU_CLKSEL_CON6]
116 mov x5, PMU_BASE
[all …]
/rk3399_ARM-atf/plat/nxp/soc-ls1043a/aarch64/
H A Dls1043a.S158 mov x5, x30
189 mov x30, x5
297 mov x5, xzr
307 orr x4, x5, #DEVDISR5_I2C_1
309 csel x5, x5, x4, EQ
311 orr x4, x5, #DEVDISR5_LPUART1
313 csel x5, x5, x4, EQ
315 orr x4, x5, #DEVDISR5_FLX_TMR
317 csel x5, x5, x4, EQ
319 orr x4, x5, #DEVDISR5_OCRAM1
[all …]
/rk3399_ARM-atf/common/aarch64/
H A Ddebug.S40 mov x5, #MAX_DEC_DIVISOR
42 udiv x0, x4, x5 /* Get the quotient */
43 msub x4, x0, x5, x4 /* Find the remainder */
46 udiv x5, x5, x6 /* Reduce divisor */
47 cbnz x5, dec_print_loop
66 mov x5, x0
78 mov x4, x5
117 mov x5, #64 /* No of bits to convert to ascii */
123 sub x5, x5, #4
124 lsrv x0, x4, x5
[all …]
/rk3399_ARM-atf/plat/marvell/armada/a8k/common/aarch64/
H A Dplat_helpers.S92 mrs x5, s3_1_c11_c0_2 /* L2 Ctrl */
93 orr x5, x5, #(1 << 21) /* Enable L1/L2 cache ECC & Parity */
94 msr s3_1_c11_c0_2, x5 /* L2 Ctrl */
103 mrs x5, s3_1_c15_c0_0 /* L2 Ctrl */
104 orr x5, x5, #(1 << 14) /* Enable UniqueClean evictions with data */
105 msr s3_1_c15_c0_0, x5 /* L2 Ctrl */
/rk3399_ARM-atf/plat/nxp/common/psci/aarch64/
H A Dpsci_utils.S36 stp x4, x5, [sp, #-16]!
193 ldp x4, x5, [sp], #16
218 stp x4, x5, [sp, #-16]!
274 ldp x4, x5, [sp], #16
317 stp x4, x5, [sp, #-16]!
359 ldp x4, x5, [sp], #16
409 stp x4, x5, [sp, #-16]!
412 mov x5, x0 /* x5 = core mask */
415 mov x0, x5
432 mov x0, x5
[all …]
/rk3399_ARM-atf/plat/rockchip/common/pmusram/
H A Dcpus_on_fixed_addr.S23 adr x5, sys_sleep_flag_sram
24 ldr w2, [x5, #PSRAM_DT_PM_FLAG]
30 adr x5, sys_sleep_flag_sram
31 ldr x1, [x5, #PSRAM_DT_SP]
34 ldr x1, [x5, #PSRAM_DT_DDR_FUNC]
/rk3399_ARM-atf/plat/intel/soc/common/
H A Dsocfpga_sip_svc.c1101 u_register_t x5, x6, x7, x8, x9, x10, x11; local
1104 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1113 smc_fid, x1, x2, x3, x4, x5);
1451 resp_payload_addr = (uint32_t *)x5;
1559 x5, x6, x7, (uint32_t *) &x8,
1563 x5, x6, x7, (uint32_t *) &x8,
1734 status = intel_fcs_aes_crypt_init(x2, x3, x4, x5,
1747 x3, x4, x5, x6, x7, x8, is_final,
1754 status = intel_fcs_get_digest_init(x2, x3, x4, x5, x6,
1766 x3, x4, x5, x6, (uint32_t *) &x7,
[all …]
/rk3399_ARM-atf/plat/nxp/soc-ls1046a/aarch64/
H A Dls1046a.S128 mov x5, x30
169 mov x30, x5
359 mov x5, #NXP_TIMER_ADDR
360 ldr w4, [x5, #SYS_COUNTER_CNTCR_OFFSET]
368 str w4, [x5, #SYS_COUNTER_CNTCR_OFFSET]
371 mov x5, x0
374 ldr w3, [x5, #GICC_CTLR_OFFSET]
377 str w3, [x5, #GICC_CTLR_OFFSET]
395 ldr w2, [x5, #GICC_PMR_OFFSET]
397 str w2, [x5, #GICC_PMR_OFFSET]
[all …]
/rk3399_ARM-atf/plat/qti/common/src/
H A Dqti_syscall.c180 u_register_t x5 = read_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X5); in qti_sip_mem_assign() local
183 x5 = (uint32_t) x5; in qti_sip_mem_assign()
186 if ((x1 != QTI_SIP_SVC_MEM_ASSIGN_PARAM_ID) || (x5 == 0x0)) { in qti_sip_mem_assign()
192 dyn_map_start = x5; in qti_sip_mem_assign()
204 x6 = *((uint32_t *) x5 + 1); in qti_sip_mem_assign()
205 x7 = *((uint32_t *) x5 + 2); in qti_sip_mem_assign()
206 x5 = *(uint32_t *) x5; in qti_sip_mem_assign()
208 x6 = *((uint64_t *) x5 + 1); in qti_sip_mem_assign()
209 x7 = *((uint64_t *) x5 + 2); in qti_sip_mem_assign()
210 x5 = *(uint64_t *) x5; in qti_sip_mem_assign()
[all …]
/rk3399_ARM-atf/plat/nxp/common/ocram/aarch64/
H A Docram.S28 stp x4, x5, [sp, #-16]!
41 ldp x4, x5, [x0]
45 stp x4, x5, [x0]
69 ldp x4, x5, [sp], #16
/rk3399_ARM-atf/plat/intel/soc/common/aarch64/
H A Dplat_helpers.S178 ldr x5, =L2_RESET_DONE_STATUS
179 cmp x1, x5
183 ldr x5, =SMP_SEC_CORE_BOOT_REQ
184 cmp x1, x5
204 ldr x5, [x4]
207 mov x2, x5
210 and x5, x5, #BS_REG_MAGIC_KEYS_MASK
214 cmp x1, x5
/rk3399_ARM-atf/lib/xlat_tables_v2/aarch64/
H A Denable_mmu.S73 mov_imm x5, SCTLR_WXN_BIT | SCTLR_C_BIT | SCTLR_M_BIT
74 orr x4, x4, x5
77 bic x5, x4, #SCTLR_C_BIT
79 csel x4, x5, x4, ne
/rk3399_ARM-atf/plat/rockchip/rk3399/
H A Dplat_sip_calls.c60 uint64_t x5, x6; in rockchip_plat_sip_handler() local
70 x5 = read_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X5); in rockchip_plat_sip_handler()
72 SMC_RET1(handle, dp_hdcp_store_key(x1, x2, x3, x4, x5, x6)); in rockchip_plat_sip_handler()
/rk3399_ARM-atf/plat/nxp/soc-ls1028a/aarch64/
H A Dls1028a.S67 stp x4, x5, [sp, #-16]!
91 ldp x4, x5, [sp], #16
233 mov x5, #NXP_GICD_ADDR
234 ldr w2, [x5, #GICD_CTLR_OFFSET]
236 str w2, [x5, #GICD_CTLR_OFFSET]
242 ldr w2, [x5, #GICD_CTLR_OFFSET]
314 mov x5, x0
324 str w3, [x5, #GICR_ICENABLER0_OFFSET]
340 ldr w4, [x5, #GICR_IGROUPR0_OFFSET]
342 str w4, [x5, #GICR_IGROUPR0_OFFSET]
[all …]
/rk3399_ARM-atf/bl31/aarch64/
H A Dea_delegate.S243 ldr x5, [sp, #CTX_EL3STATE_OFFSET + CTX_DOUBLE_FAULT_ESR]
244 cbz x5, 1f
258 mrs x5, esr_el3
259 str x5, [sp, #CTX_EL3STATE_OFFSET + CTX_DOUBLE_FAULT_ESR]
275 ldr x5, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
277 mov sp, x5
/rk3399_ARM-atf/plat/nxp/soc-ls1088a/aarch64/
H A Dls1088a.S111 stp x4, x5, [sp, #-16]!
135 ldp x4, x5, [sp], #16
278 mov x5, #NXP_GICD_ADDR
279 ldr w2, [x5, #GICD_CTLR_OFFSET]
281 str w2, [x5, #GICD_CTLR_OFFSET]
286 ldr w2, [x5, #GICD_CTLR_OFFSET]
358 mov x5, x0
367 str w3, [x5, #GICR_ICENABLER0_OFFSET]
383 ldr w4, [x5, #GICR_IGROUPR0_OFFSET]
385 str w4, [x5, #GICR_IGROUPR0_OFFSET]
[all …]
/rk3399_ARM-atf/plat/nxp/soc-lx2160a/aarch64/
H A Dlx2160a.S84 stp x4, x5, [sp, #-16]!
112 ldp x4, x5, [sp], #16
266 mov x5, #NXP_GICD_ADDR
267 ldr w2, [x5, #GICD_CTLR_OFFSET]
269 str w2, [x5, #GICD_CTLR_OFFSET]
275 ldr w2, [x5, #GICD_CTLR_OFFSET]
348 mov x5, x0
357 str w3, [x5, #GICR_ICENABLER0_OFFSET]
373 ldr w4, [x5, #GICR_IGROUPR0_OFFSET]
375 str w4, [x5, #GICR_IGROUPR0_OFFSET]
[all …]
H A Dlx2160a_warm_rst.S117 mov x5, xzr
119 add x5, x5, #1
120 cmp x5, #COUNT_100
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/dp/
H A Dcdn_dp.c54 uint64_t x5, in dp_hdcp_store_key() argument
65 hdcp_key_pdata[4] = x5; in dp_hdcp_store_key()
/rk3399_ARM-atf/drivers/nxp/console/
H A Dlinflex_console.S70 ubfx x5, x5, #UARTCR_OSR_SHIFT, #UARTCR_OSR_WIDTH
93 mov x5, x1
95 udiv x6, x5, x4
97 msub x7, x6, x4, x5
/rk3399_ARM-atf/include/lib/el3_runtime/aarch64/
H A Dcontext.h407 #define set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5) do { \ argument
408 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X5, x5); \
411 #define set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6) do { \ argument
413 set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5); \
415 #define set_aapcs_args7(ctx, x0, x1, x2, x3, x4, x5, x6, x7) do { \ argument
417 set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6); \
/rk3399_ARM-atf/plat/arm/board/arm_fpga/aarch64/
H A Dfpga_helpers.S69 mov x5, #VALID_MPID
145 mov x5, #FPGA_MAX_PE_PER_CPU
149 madd x0, x1, x5, x0
/rk3399_ARM-atf/plat/marvell/armada/common/
H A Dmrvl_sip_svc.c82 u_register_t ret, read, x5 = x1; in mrvl_sip_smc_handler() local
96 x5 = x1 + COMPHY_TRX_TRAIN_CTRL_REG_0_OFFS; in mrvl_sip_smc_handler()
111 ret = mvebu_cp110_comphy_power_on(x1, x2, x3, x5); in mrvl_sip_smc_handler()
/rk3399_ARM-atf/lib/cpus/aarch64/
H A Dcpu_helpers.S69 adr_l x5, (__CPU_OPS_END__ + CPU_MIDR)
79 cmp x4, x5

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