1*10b1e13bSJiafei Pan/* 2*10b1e13bSJiafei Pan * Copyright 2021 NXP 3*10b1e13bSJiafei Pan * 4*10b1e13bSJiafei Pan * SPDX-License-Identifier: BSD-3-Clause 5*10b1e13bSJiafei Pan */ 6*10b1e13bSJiafei Pan 7*10b1e13bSJiafei Pan#include <asm_macros.S> 8*10b1e13bSJiafei Pan 9*10b1e13bSJiafei Pan#include <soc_default_base_addr.h> 10*10b1e13bSJiafei Pan#include <soc_default_helper_macros.h> 11*10b1e13bSJiafei Pan 12*10b1e13bSJiafei Pan.global ocram_init 13*10b1e13bSJiafei Pan 14*10b1e13bSJiafei Pan/* 15*10b1e13bSJiafei Pan * void ocram_init(uintptr_t start_addr, size_t size) 16*10b1e13bSJiafei Pan * 17*10b1e13bSJiafei Pan * This function will do OCRAM ECC. 18*10b1e13bSJiafei Pan * OCRAM is initialized with 64-bit writes and then a write 19*10b1e13bSJiafei Pan * performed to address 0x0010_0534 with the value 0x0000_0008. 20*10b1e13bSJiafei Pan * 21*10b1e13bSJiafei Pan * x0: start_addr 22*10b1e13bSJiafei Pan * x1: size in bytes 23*10b1e13bSJiafei Pan * Called from C 24*10b1e13bSJiafei Pan */ 25*10b1e13bSJiafei Pan 26*10b1e13bSJiafei Panfunc ocram_init 27*10b1e13bSJiafei Pan /* save the aarch32/64 non-volatile registers */ 28*10b1e13bSJiafei Pan stp x4, x5, [sp, #-16]! 29*10b1e13bSJiafei Pan stp x6, x7, [sp, #-16]! 30*10b1e13bSJiafei Pan stp x8, x9, [sp, #-16]! 31*10b1e13bSJiafei Pan stp x10, x11, [sp, #-16]! 32*10b1e13bSJiafei Pan stp x12, x13, [sp, #-16]! 33*10b1e13bSJiafei Pan stp x18, x30, [sp, #-16]! 34*10b1e13bSJiafei Pan 35*10b1e13bSJiafei Pan /* convert bytes to 64-byte chunks */ 36*10b1e13bSJiafei Pan lsr x1, x1, #6 37*10b1e13bSJiafei Pan1: 38*10b1e13bSJiafei Pan /* for each location, read and write-back */ 39*10b1e13bSJiafei Pan dc ivac, x0 40*10b1e13bSJiafei Pan dsb sy 41*10b1e13bSJiafei Pan ldp x4, x5, [x0] 42*10b1e13bSJiafei Pan ldp x6, x7, [x0, #16] 43*10b1e13bSJiafei Pan ldp x8, x9, [x0, #32] 44*10b1e13bSJiafei Pan ldp x10, x11, [x0, #48] 45*10b1e13bSJiafei Pan stp x4, x5, [x0] 46*10b1e13bSJiafei Pan stp x6, x7, [x0, #16] 47*10b1e13bSJiafei Pan stp x8, x9, [x0, #32] 48*10b1e13bSJiafei Pan stp x10, x11, [x0, #48] 49*10b1e13bSJiafei Pan dc cvac, x0 50*10b1e13bSJiafei Pan 51*10b1e13bSJiafei Pan sub x1, x1, #1 52*10b1e13bSJiafei Pan cbz x1, 2f 53*10b1e13bSJiafei Pan add x0, x0, #64 54*10b1e13bSJiafei Pan b 1b 55*10b1e13bSJiafei Pan2: 56*10b1e13bSJiafei Pan /* Clear OCRAM ECC status bit in SBEESR2 and MBEESR2 */ 57*10b1e13bSJiafei Pan ldr w1, =OCRAM_EESR_MASK 58*10b1e13bSJiafei Pan ldr x0, =DCFG_SBEESR2_ADDR 59*10b1e13bSJiafei Pan str w1, [x0] 60*10b1e13bSJiafei Pan ldr x0, =DCFG_MBEESR2_ADDR 61*10b1e13bSJiafei Pan str w1, [x0] 62*10b1e13bSJiafei Pan 63*10b1e13bSJiafei Pan /* restore the aarch32/64 non-volatile registers */ 64*10b1e13bSJiafei Pan ldp x18, x30, [sp], #16 65*10b1e13bSJiafei Pan ldp x12, x13, [sp], #16 66*10b1e13bSJiafei Pan ldp x10, x11, [sp], #16 67*10b1e13bSJiafei Pan ldp x8, x9, [sp], #16 68*10b1e13bSJiafei Pan ldp x6, x7, [sp], #16 69*10b1e13bSJiafei Pan ldp x4, x5, [sp], #16 70*10b1e13bSJiafei Pan ret 71*10b1e13bSJiafei Panendfunc ocram_init 72