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Searched refs:x3 (Results 1 – 25 of 269) sorted by relevance

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/rk3399_ARM-atf/plat/imx/common/
H A Dimx_sip_svc.c27 u_register_t x3, in imx_sip_handler() argument
35 SMC_RET1(handle, imx_kernel_entry_handler(smc_fid, x1, x2, x3, x4)); in imx_sip_handler()
46 return dram_dvfs_handler(smc_fid, handle, x1, x2, x3); in imx_sip_handler()
50 SMC_RET1(handle, imx_soc_info_handler(smc_fid, x1, x2, x3)); in imx_sip_handler()
53 SMC_RET1(handle, imx_gpc_handler(smc_fid, x1, x2, x3)); in imx_sip_handler()
56 return dram_dvfs_handler(smc_fid, handle, x1, x2, x3); in imx_sip_handler()
60 return dram_dvfs_handler(smc_fid, handle, x1, x2, x3); in imx_sip_handler()
62 SMC_RET1(handle, imx_gpc_handler(smc_fid, x1, x2, x3)); in imx_sip_handler()
67 return imx_srtc_handler(smc_fid, handle, x1, x2, x3, x4); in imx_sip_handler()
69 SMC_RET1(handle, imx_cpufreq_handler(smc_fid, x1, x2, x3)); in imx_sip_handler()
[all …]
H A Dimx_sip_handler.c52 u_register_t x3, in imx_srtc_handler() argument
59 ret = imx_srtc_set_time(x2, x3, x4); in imx_srtc_handler()
88 u_register_t x3) in imx_cpufreq_handler() argument
92 imx_cpufreq_set_target(x2, x3); in imx_cpufreq_handler()
111 u_register_t x3) in imx_wakeup_src_handler() argument
156 u_register_t x3, in imx_misc_set_temp_handler() argument
159 return sc_misc_set_temp(ipc_handle, x1, x2, x3, x4); in imx_misc_set_temp_handler()
168 u_register_t x3, in imx_src_handler() argument
248 u_register_t x3, in imx_src_handler() argument
266 u_register_t x3, in imx_get_commit_hash() argument
[all …]
/rk3399_ARM-atf/plat/hisilicon/hikey/
H A Dhisi_pwrc_sram.S29 mrs x3, actlr_el3
30 orr x3, x3, #ACTLR_EL3_L2ECTLR_BIT
31 msr actlr_el3, x3
33 mrs x3, actlr_el2
34 orr x3, x3, #ACTLR_EL2_L2ECTLR_BIT
35 msr actlr_el2, x3
37 ldr x3, =PWRCTRL_ACPU_ASM_D_ARM_PARA_AD
42 pen: ldr x4, [x3, x0, LSL #3]
48 mov x3, #0x0
/rk3399_ARM-atf/plat/imx/common/include/
H A Dimx_sip_svc.h53 u_register_t x2, u_register_t x3,
62 u_register_t x2, u_register_t x3);
64 u_register_t x2, u_register_t x3);
67 u_register_t x1, u_register_t x2, u_register_t x3);
70 u_register_t x1, u_register_t x2, u_register_t x3) in dram_dvfs_handler() argument
76 u_register_t x2, u_register_t x3, u_register_t x4);
80 u_register_t x1, u_register_t x2, u_register_t x3);
83 u_register_t x2, u_register_t x3);
90 u_register_t x2, u_register_t x3, void *handle);
95 u_register_t x2, u_register_t x3, u_register_t x4);
[all …]
/rk3399_ARM-atf/lib/libc/aarch64/
H A Dmemset.S22 mov x3, x0 /* keep x0 */
28 strb w1, [x3], #1
31 tst x3, #7
45 stp x1, x1, [x3], #16 /* write 64 bytes in a loop */
50 stp x1, x1, [x3], #16 /* write 32 bytes */
51 stp x1, x1, [x3], #16
53 stp x1, x1, [x3], #16 /* write 16 bytes */
55 str x1, [x3], #8 /* write 8 bytes */
57 str w1, [x3], #4 /* write 4 bytes */
59 strh w1, [x3], #2 /* write 2 bytes */
[all …]
/rk3399_ARM-atf/plat/nxp/soc-ls1028a/aarch64/
H A Dls1028a.S151 mov x3, x30
163 mov x30, x3
176 mov x3, x30
197 mov x30, x3
366 mrs x3, osdlr_el1
367 orr x3, x3, #OSDLR_EL1_DLK_LOCK
368 msr osdlr_el1, x3
372 mov x3, #ICC_IGRPEN0_EL1_EN
373 msr ICC_IGRPEN0_EL1, x3
386 ldr x3, =NXP_TIMER_ADDR
[all …]
/rk3399_ARM-atf/plat/nxp/common/aarch64/
H A Dbl31_data.S161 clz x3, x0
163 sub x0, x0, x3
173 ldr x3, =BC_PSCI_BASE
174 add x3, x3, x1
184 mov x3, #SEC_REGION_SIZE
185 mul x3, x3, x0
192 sub x1, x3, x1
197 ldr x3, =SECONDARY_TOP
200 sub x3, x3, x1
206 str x2, [x3]
[all …]
/rk3399_ARM-atf/services/std_svc/
H A Dstd_svc_setup.c119 u_register_t x3 = x3_arg; in std_svc_smc_handler() local
127 x3 &= UINT32_MAX; in std_svc_smc_handler()
150 ret = psci_smc_handler(smc_fid, x1, x2, x3, x4, in std_svc_smc_handler()
168 return spm_mm_smc_handler(smc_fid, x1, x2, x3, x4, cookie, in std_svc_smc_handler()
179 return spmd_ffa_smc_handler(smc_fid, x1, x2, x3, x4, cookie, in std_svc_smc_handler()
186 return sdei_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, in std_svc_smc_handler()
193 return trng_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, in std_svc_smc_handler()
200 return errata_abi_smc_handler(smc_fid, x1, x2, x3, x4, cookie, in std_svc_smc_handler()
208 return rmmd_rmm_el3_handler(smc_fid, x1, x2, x3, x4, cookie, in std_svc_smc_handler()
213 return rmmd_rmi_handler(smc_fid, x1, x2, x3, x4, cookie, in std_svc_smc_handler()
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/emi/
H A Demi_ctrl.c73 u_register_t x3, in sip_emidbg_control() argument
87 ret = emi_mpu_read_by_type((unsigned int)x2, (unsigned int)x3, in sip_emidbg_control()
104 ret = emi_clear_violation((unsigned int)x2, (unsigned int)x3); in sip_emidbg_control()
109 ret = slc_parity_select((unsigned int)x2, (unsigned int)x3); in sip_emidbg_control()
125 u_register_t x3, in sip_emimpu_control() argument
134 ret = emi_mpu_set_protection((uint32_t)x2, (uint32_t)x3, (unsigned int)x4); in sip_emimpu_control()
137 ret = emi_mpu_set_aid((unsigned int)x2, (unsigned int)x3); in sip_emimpu_control()
140 ret = emi_mpu_read_by_type((unsigned int)x2, (unsigned int)x3, in sip_emimpu_control()
144 ret = emi_kp_set_protection((size_t)x2, (size_t)x3, (unsigned int)x4); in sip_emimpu_control()
159 u_register_t x3, in sip_tee_emimpu_control() argument
[all …]
/rk3399_ARM-atf/plat/nxp/soc-ls1088a/aarch64/
H A Dls1088a.S174 mov x3, x30
185 mov x30, x3
217 mov x3, x30
242 mov x30, x3
410 mrs x3, osdlr_el1
411 orr x3, x3, #OSDLR_EL1_DLK_LOCK
412 msr osdlr_el1, x3
416 mov x3, #ICC_IGRPEN0_EL1_EN
417 msr ICC_IGRPEN0_EL1, x3
430 ldr x3, =NXP_TIMER_ADDR
[all …]
/rk3399_ARM-atf/plat/arm/board/arm_fpga/aarch64/
H A Dfpga_helpers.S80 ldr x3, [x1, x0, LSL #PLAT_FPGA_HOLD_ENTRY_SHIFT]
81 cmp x3, #PLAT_FPGA_HOLD_STATE_GO
86 ldr x3, [x2]
87 br x3
136 lsl x3, x0, #MPIDR_AFFINITY_BITS
137 csel x3, x3, x0, eq
140 ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
141 ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
142 ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
/rk3399_ARM-atf/plat/arm/board/automotive_rd/platform/rdaspen/include/
H A Drdaspen_helpers.S36 lsl x3, x0, #MPIDR_AFFINITY_BITS
37 csel x3, x3, x0, eq
40 ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
41 ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
42 ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
/rk3399_ARM-atf/plat/mediatek/common/
H A Dmtk_sip_svc.c28 u_register_t x3, in mediatek_plat_sip_handler() argument
43 u_register_t x3, in mediatek_sip_handler() argument
52 clean_top_32b_of_param(smc_fid, &x1, &x2, &x3, &x4); in mediatek_sip_handler()
74 boot_to_kernel(x1, x2, x3, x4); in mediatek_sip_handler()
83 return mediatek_plat_sip_handler(smc_fid, x1, x2, x3, x4, in mediatek_sip_handler()
94 u_register_t x3, in sip_smc_handler() argument
116 return mediatek_sip_handler(smc_fid, x1, x2, x3, x4, in sip_smc_handler()
/rk3399_ARM-atf/plat/amd/versal2/aarch64/
H A Dhelpers.S62 mov x3, x0
65 cmp x0, x3
96 ldr x3, =plat_cores_per_cluster
97 ldr w0, [x3]
102 ldr x3, =plat_cluster_count
103 ldr w3, [x3]
104 cmp x1, x3
/rk3399_ARM-atf/plat/arm/board/corstone1000/common/
H A Dcorstone1000_helpers.S38 ubfx x3, x0, #MPIDR_AFF3_SHIFT, #MPIDR_AFFINITY_BITS
41 lsl x3, x3, #MPIDR_AFFINITY_BITS
42 orr x3, x3, x2
46 madd x0, x3, x4, x1
/rk3399_ARM-atf/lib/aarch64/
H A Dcache_helpers.S41 dcache_line_size x2, x3
43 sub x3, x2, #1
44 bic x0, x0, x3
59 dcache_line_size x2, x3
60 sub x3, x2, #1
61 bic x0, x0, x3
75 mov x3, x30
78 mov x30, x3
164 ubfx x3, x9, \shift, \fw
165 lsl x3, x3, \ls
[all …]
H A Dmisc_helpers.S152 block_size .req x3 /* Size of a block in bytes as read in DCZID_EL0 */
386 orr x3, x0, x1
387 tst x3, #0xf
394 ldp x3, x4, [x1], #16
395 stp x3, x4, [x0], #16
505 1: ldr x3, [x1]
508 cmp x3, x6
512 cmp x3, x7
514 add x3, x3, x0
515 str x3, [x1]
[all …]
/rk3399_ARM-atf/lib/pmf/
H A Dpmf_smc.c20 u_register_t x3, in pmf_smc_handler() argument
37 x3 = (uint32_t)x3; in pmf_smc_handler()
48 (unsigned int)x3, &ts_value); in pmf_smc_handler()
66 (unsigned int)x3, &ts_value); in pmf_smc_handler()
/rk3399_ARM-atf/plat/arm/common/
H A Darm_sip_svc.c56 u_register_t x3, in arm_sip_handler() argument
72 return pmf_smc_handler(smc_fid, x1, x2, x3, x4, cookie, in arm_sip_handler()
82 return debugfs_smc_handler(smc_fid, x1, x2, x3, x4, cookie, in arm_sip_handler()
91 return ethosn_smc_handler(smc_fid, x1, x2, x3, x4, cookie, in arm_sip_handler()
109 (uint32_t) x1, (uint32_t) x2, (uint32_t) x3, in arm_sip_handler()
148 return plat_arm_sip_handler(smc_fid, x1, x2, x3, x4, in arm_sip_handler()
/rk3399_ARM-atf/plat/mediatek/mt8195/
H A Dplat_sip_calls.c21 u_register_t x3, in mediatek_plat_sip_handler() argument
33 ret = emi_mpu_sip_handler(x1, x2, x3); in mediatek_plat_sip_handler()
43 ret = spm_vcorefs_v2_args(x1, x2, x3, &x4); in mediatek_plat_sip_handler()
48 ret = dfd_smc_dispatcher(x1, x2, x3, x4); in mediatek_plat_sip_handler()
53 ret = apusys_kernel_ctrl(x1, x2, x3, x4, &ret_val); in mediatek_plat_sip_handler()
/rk3399_ARM-atf/services/el3/
H A Dven_el3_svc.c48 u_register_t x3, in ven_el3_svc_handler() argument
60 return debugfs_smc_handler(smc_fid, x1, x2, x3, x4, cookie, in ven_el3_svc_handler()
72 return pmf_smc_handler(smc_fid, x1, x2, x3, x4, cookie, in ven_el3_svc_handler()
83 return plat_arm_acs_smc_handler(smc_fid, x1, x2, x3, x4, handle); in ven_el3_svc_handler()
101 return spm_mm_tpm_start_handler(smc_fid, x1, x2, x3, x4, cookie, in ven_el3_svc_handler()
/rk3399_ARM-atf/plat/arm/board/tc/include/
H A Dtc_helpers.S41 lsl x3, x0, #MPIDR_AFFINITY_BITS
42 csel x3, x3, x0, eq
45 ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
46 ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
47 ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
/rk3399_ARM-atf/plat/mediatek/mt8186/
H A Dplat_sip_calls.c19 u_register_t x3, in mediatek_plat_sip_handler() argument
30 ret = spm_vcorefs_args(x1, x2, x3, (uint64_t *)&x4); in mediatek_plat_sip_handler()
35 ret = dfd_smc_dispatcher(x1, x2, x3, x4); in mediatek_plat_sip_handler()
40 ret = msdc_smc_dispatcher(x1, x2, x3, x4); in mediatek_plat_sip_handler()
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t194/
H A Dplat_trampoline.S49 ldp x3, x4, [x1], #16
50 stp x3, x4, [x0], #16
135 mov x3, #MC_SECURITY_CFG3_0
136 ldr w1, [x0, x3]
138 mov x3, #MC_SECURITY_CFG0_0
139 ldr w2, [x0, x3]
140 orr x3, x1, x2 /* TZDRAM base */
147 str x0, [x3, x2] /* set value in TZDRAM */
/rk3399_ARM-atf/plat/mediatek/mt8192/
H A Dplat_sip_calls.c18 u_register_t x3, in mediatek_plat_sip_handler() argument
30 ret = spm_vcorefs_args(x1, x2, x3, (uint64_t *)&x4); in mediatek_plat_sip_handler()
35 ret = apusys_kernel_ctrl(x1, x2, x3, x4, &rnd_val0); in mediatek_plat_sip_handler()
40 ret = dfd_smc_dispatcher(x1, x2, x3, x4); in mediatek_plat_sip_handler()

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