Lines Matching refs:x3
52 uint64_t x3, in socfpga_sip_handler() argument
1094 u_register_t x3, argument
1114 smc_fid, x1, x2, x3, x4, x5);
1215 uint32_t comb_addr_mode = (uint32_t)x3;
1238 uint32_t qspi_nwords = (uint32_t)x3;
1274 uint32_t qspi_total_nwords = (((uint32_t)x3) / MBOX_WORD_BYTE);
1326 (uint32_t *)x3,
1441 cmd_payload_addr = (uint32_t *)x3;
1477 uint32_t context_id = (uint32_t)x3;
1523 status = intel_fcs_cntr_set_preauth(smc_fid, x1, x2, x3,
1544 status = intel_fcs_get_attestation_cert(smc_fid, x1, x2, x3,
1559 status = intel_fcs_encryption_ext(smc_fid, x1, x2, x3,
1563 status = intel_fcs_decryption_ext(smc_fid, x1, x2, x3,
1575 status = intel_fcs_send_cert(smc_fid, x1, x2, x3, &mbox_error);
1612 uint32_t key_len_words = (uint32_t)x3 / MBOX_WORD_BYTE;
1637 uint32_t key_len_words = (uint32_t)x3 / MBOX_WORD_BYTE;
1660 uint32_t key_uid = (uint32_t)x3;
1688 uint32_t key_uid = (uint32_t)x3;
1708 uint32_t key_uid = (uint32_t)x3;
1735 status = intel_fcs_aes_crypt_init(x2, x3, x4, x5,
1748 x3, x4, x5, x6, x7, x8, is_final,
1755 status = intel_fcs_get_digest_init(x2, x3, x4, x5, x6,
1767 x3, x4, x5, x6, (uint32_t *) &x7,
1775 status = intel_fcs_mac_verify_init(x2, x3, x4, x5, x6,
1787 x3, x4, x5, x6, (uint32_t *) &x7, x8,
1794 status = intel_fcs_ecdsa_hash_sign_init(x2, x3, x4, x5, x6,
1801 status = intel_fcs_ecdsa_hash_sign_finalize(smc_fid, x1, x2, x3,
1809 status = intel_fcs_ecdsa_sha2_data_sign_init(x2, x3, x4, x5, x6,
1821 x1, x2, x3, x4, x5, x6, (uint32_t *) &x7,
1828 status = intel_fcs_ecdsa_hash_sig_verify_init(x2, x3, x4, x5,
1836 x2, x3, x4, x5, x6, (uint32_t *) &x7,
1843 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x2, x3, x4,
1856 smc_fid, x1, x2, x3, x4, x5, x6,
1864 status = intel_fcs_ecdsa_get_pubkey_init(x2, x3, x4, x5, x6,
1871 status = intel_fcs_ecdsa_get_pubkey_finalize(smc_fid, x1, x2, x3,
1878 status = intel_fcs_ecdh_request_init(x2, x3, x4, x5, x6,
1890 status = intel_fcs_ecdh_request_finalize(smc_fid, x1, x2, x3,
1899 uint32_t src_size = (uint32_t)x3;
1917 status = intel_fcs_hkdf_request(smc_fid, x1, x2, x3, x4, x5, x6,
1923 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4,
1936 u_register_t x3, argument
2013 (uint32_t)x3, &retval);
2085 status = intel_smc_service_completed(x1, x2, x3, &rcv_id,
2096 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, x5, x6,
2108 status = intel_fcs_decryption(x2, x3, x4, x5, &send_id);
2110 status = intel_fcs_encryption(x2, x3, x4, x5, &send_id);
2122 if (x3 == FCS_MODE_DECRYPT) {
2125 } else if (x3 == FCS_MODE_ENCRYPT) {
2140 status = intel_fcs_random_number_gen_ext(x1, x2, x3,
2153 status = intel_fcs_cntr_set_preauth(smc_fid, 0, x1, x2, x3,
2178 status = intel_fcs_attestation_subkey(x1, x2, x3,
2180 SMC_RET4(handle, status, mbox_error, x3, x4);
2183 status = intel_fcs_get_measurement(x1, x2, x3,
2185 SMC_RET4(handle, status, mbox_error, x3, x4);
2189 (uint32_t *) &x3, &mbox_error);
2190 SMC_RET4(handle, status, mbox_error, x2, x3);
2209 status = intel_fcs_export_crypto_service_key(x1, x2, x3,
2211 SMC_RET4(handle, status, mbox_error, x3, x4);
2219 status = intel_fcs_get_crypto_service_key_info(x1, x2, x3,
2221 SMC_RET4(handle, status, mbox_error, x3, x4);
2225 status = intel_fcs_get_digest_init(x1, x2, x3,
2233 x3, x4, x5, (uint32_t *) &x6, false,
2241 x3, x4, x5, (uint32_t *) &x6, true,
2248 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3,
2256 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3,
2263 status = intel_fcs_mac_verify_init(x1, x2, x3,
2272 x3, x4, x5, (uint32_t *) &x6, x7, false,
2281 x3, x4, x5, (uint32_t *) &x6, x7, true,
2289 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3,
2298 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3,
2305 status = intel_fcs_ecdsa_sha2_data_sign_init(x1, x2, x3,
2313 0, x1, x2, x3, x4, x5, (uint32_t *) &x6,
2321 0, x1, x2, x3, x4, x5, (uint32_t *) &x6,
2329 x2, x3, x4, x5, (uint32_t *) &x6, false,
2337 x2, x3, x4, x5, (uint32_t *) &x6, true,
2343 status = intel_fcs_ecdsa_hash_sign_init(x1, x2, x3,
2351 x3, x4, x5, (uint32_t *) &x6,
2357 status = intel_fcs_ecdsa_hash_sig_verify_init(x1, x2, x3,
2365 x2, x3, x4, x5, (uint32_t *) &x6,
2371 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x1, x2, x3,
2380 smc_fid, 0, x1, x2, x3, x4, x5,
2390 x1, x2, x3, x4, x5, (uint32_t *) &x6,
2399 x1, x2, x3, x4, x5, (uint32_t *) &x6,
2408 smc_fid, 0, x1, x2, x3, x4, x5,
2415 status = intel_fcs_ecdsa_get_pubkey_init(x1, x2, x3,
2422 x1, x2, x3, (uint32_t *) &x4, &mbox_error);
2423 SMC_RET4(handle, status, mbox_error, x3, x4);
2427 status = intel_fcs_ecdh_request_init(x1, x2, x3,
2434 status = intel_fcs_ecdh_request_finalize(smc_fid, 0, x1, x2, x3,
2440 status = intel_fcs_aes_crypt_init(x1, x2, x3, x4, x5,
2448 x3, x4, x5, x6, 0, false, &send_id, 0, 0);
2455 x3, x4, x5, x6, 0, true, &send_id, 0, 0);
2498 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4,
2506 u_register_t x3, argument
2516 return sip_smc_handler_v2(smc_fid, x1, x2, x3, x4,
2522 uintptr_t ret = sip_smc_handler_v3(smc_fid, x1, x2, x3, x4,
2528 return sip_smc_handler_v1(smc_fid, x1, x2, x3, x4,