1/* 2 * Copyright (c) 2021-2024 Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <platform_def.h> 10 11 .globl plat_secondary_cold_boot_setup 12 .globl plat_get_my_entrypoint 13 .globl plat_is_my_cpu_primary 14 .globl plat_arm_calc_core_pos 15 16 /* -------------------------------------------------------------------- 17 * void plat_secondary_cold_boot_setup (void); 18 * 19 * For AArch32, cold-booting secondary CPUs is not yet 20 * implemented and they panic. 21 * -------------------------------------------------------------------- 22 */ 23func plat_secondary_cold_boot_setup 24#if defined(CORSTONE1000_FVP_MULTICORE) 25 26 /* Calculate the address of our hold entry */ 27 bl plat_my_core_pos 28 lsl x0, x0, #CORSTONE1000_SECONDARY_CORE_HOLD_SHIFT 29 mov_imm x2, CORSTONE1000_SECONDARY_CORE_HOLD_BASE 30 31 /* Set the wait state for the secondary core */ 32 mov_imm x3, CORSTONE1000_SECONDARY_CORE_STATE_WAIT 33 str x3, [x2, x0] 34 dmb ish 35 36 /* Poll until the primary core signals to go */ 37poll_mailbox: 38 ldr x1, [x2, x0] 39 cmp x1, #CORSTONE1000_SECONDARY_CORE_STATE_WAIT 40 beq 1f 41 mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE 42 ldr x1, [x0] 43 br x1 441: 45 wfe 46 b poll_mailbox 47#else 48cb_panic: 49 b cb_panic 50#endif 51 52endfunc plat_secondary_cold_boot_setup 53 54 /* --------------------------------------------------------------------- 55 * unsigned long plat_get_my_entrypoint (void); 56 * 57 * Main job of this routine is to distinguish between a cold and warm 58 * boot. On corstone1000, this information can be queried from the power 59 * controller. The Power Control SYS Status Register (PSYSR) indicates 60 * the wake-up reason for the CPU. 61 * 62 * For a cold boot, return 0. 63 * For a warm boot, Not yet supported. 64 * 65 * TODO: PSYSR is a common register and should be 66 * accessed using locks. Since it is not possible 67 * to use locks immediately after a cold reset 68 * we are relying on the fact that after a cold 69 * reset all cpus will read the same WK field 70 * --------------------------------------------------------------------- 71 */ 72func plat_get_my_entrypoint 73 /* TODO support warm boot */ 74 /* Cold reset */ 75 mov x0, #0 76 ret 77endfunc plat_get_my_entrypoint 78 79 /* ----------------------------------------------------- 80 * unsigned int plat_is_my_cpu_primary (void); 81 * 82 * Find out whether the current CPU is the primary 83 * CPU. 84 * ----------------------------------------------------- 85 */ 86func plat_is_my_cpu_primary 87 mrs x0, mpidr_el1 88 mov_imm x1, MPIDR_AFFINITY_MASK 89 and x0, x0, x1 90 cmp x0, #CORSTONE1000_PRIMARY_CPU 91 cset w0, eq 92 ret 93endfunc plat_is_my_cpu_primary 94