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/rk3399_ARM-atf/plat/nxp/common/aarch64/
H A Dbl31_data.S37 clz x2, x0
39 sub x0, x0, x2
48 ldr x2, =BC_PSCI_BASE
49 add x2, x2, x1
58 mov x2, #SEC_REGION_SIZE
59 mul x2, x2, x0
65 sub x1, x2, x1
70 ldr x2, =SECONDARY_TOP
73 sub x2, x2, x1
77 dc ivac, x2
[all …]
/rk3399_ARM-atf/lib/compiler-rt/builtins/
H A Dpopcountdi2.c18 du_int x2 = (du_int)a; in __popcountdi2() local
19 x2 = x2 - ((x2 >> 1) & 0x5555555555555555uLL); in __popcountdi2()
21 x2 = ((x2 >> 2) & 0x3333333333333333uLL) + (x2 & 0x3333333333333333uLL); in __popcountdi2()
23 x2 = (x2 + (x2 >> 4)) & 0x0F0F0F0F0F0F0F0FuLL; in __popcountdi2()
25 su_int x = (su_int)(x2 + (x2 >> 32)); in __popcountdi2()
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t194/
H A Dplat_trampoline.S25 mov x2, #TEGRA194_STATE_SYSTEM_SUSPEND
26 lsl x2, x2, #16
27 add x2, x2, #TEGRA194_STATE_SYSTEM_SUSPEND
28 cmp x1, x2
34 mov x2, #TEGRA194_STATE_SYSTEM_RESUME
35 add x1, x1, x2
42 adr x2, __tegra194_cpu_reset_handler_data
43 ldr x2, [x2, #8]
47 cmp x2, #16
51 sub x2, x2, #16
[all …]
/rk3399_ARM-atf/plat/imx/common/
H A Dimx_sip_svc.c26 u_register_t x2, in imx_sip_handler() argument
35 SMC_RET1(handle, imx_kernel_entry_handler(smc_fid, x1, x2, x3, x4)); in imx_sip_handler()
46 return dram_dvfs_handler(smc_fid, handle, x1, x2, x3); in imx_sip_handler()
50 SMC_RET1(handle, imx_soc_info_handler(smc_fid, x1, x2, x3)); in imx_sip_handler()
53 SMC_RET1(handle, imx_gpc_handler(smc_fid, x1, x2, x3)); in imx_sip_handler()
56 return dram_dvfs_handler(smc_fid, handle, x1, x2, x3); in imx_sip_handler()
60 return dram_dvfs_handler(smc_fid, handle, x1, x2, x3); in imx_sip_handler()
62 SMC_RET1(handle, imx_gpc_handler(smc_fid, x1, x2, x3)); in imx_sip_handler()
67 return imx_srtc_handler(smc_fid, handle, x1, x2, x3, x4); in imx_sip_handler()
69 SMC_RET1(handle, imx_cpufreq_handler(smc_fid, x1, x2, x3)); in imx_sip_handler()
[all …]
H A Dimx_sip_handler.c51 u_register_t x2, in imx_srtc_handler() argument
59 ret = imx_srtc_set_time(x2, x3, x4); in imx_srtc_handler()
87 u_register_t x2, in imx_cpufreq_handler() argument
92 imx_cpufreq_set_target(x2, x3); in imx_cpufreq_handler()
110 u_register_t x2, in imx_wakeup_src_handler() argument
130 u_register_t x2) in imx_otp_handler() argument
141 ret = sc_misc_otp_fuse_write(ipc_handle, x1, x2); in imx_otp_handler()
155 u_register_t x2, in imx_misc_set_temp_handler() argument
159 return sc_misc_set_temp(ipc_handle, x1, x2, x3, x4); in imx_misc_set_temp_handler()
167 u_register_t x2, in imx_src_handler() argument
[all …]
/rk3399_ARM-atf/lib/romlib/
H A Dinit.s21 adrp x2, __DATA_RAM_END__
22 add x2, x2, :lo12:__DATA_RAM_END__
23 sub x2, x2, x0
29 adrp x2, __BSS_END__
30 add x2, x2, :lo12:__BSS_END__
31 sub x2, x2, x0
/rk3399_ARM-atf/plat/imx/common/include/
H A Dimx_sip_svc.h53 u_register_t x2, u_register_t x3,
62 u_register_t x2, u_register_t x3);
64 u_register_t x2, u_register_t x3);
67 u_register_t x1, u_register_t x2, u_register_t x3);
70 u_register_t x1, u_register_t x2, u_register_t x3) in dram_dvfs_handler() argument
76 u_register_t x2, u_register_t x3, u_register_t x4);
80 u_register_t x1, u_register_t x2, u_register_t x3);
83 u_register_t x2, u_register_t x3);
90 u_register_t x2, u_register_t x3, void *handle);
95 u_register_t x2, u_register_t x3, u_register_t x4);
[all …]
/rk3399_ARM-atf/plat/nxp/soc-ls1088a/aarch64/
H A Dls1088a.S151 mov x2, x0
158 tst x0, x2
196 ldr x2, =NXP_DCFG_ADDR
200 str w1, [x2, #DCFG_BOOTLOCPTRL_OFFSET]
204 str w1, [x2, #DCFG_BOOTLOCPTRH_OFFSET]
306 mov x2, #1
307 lsl x2, x2, x1
311 orr x2, x2, x1
313 orr x2, x2, #ICC_SGI0R_EL1_INTID
315 msr ICC_SGI0R_EL1, x2
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/emi/
H A Demi_ctrl.c72 u_register_t x2, in sip_emidbg_control() argument
87 ret = emi_mpu_read_by_type((unsigned int)x2, (unsigned int)x3, in sip_emidbg_control()
95 ret = emi_kp_clear_violation((unsigned int)x2); in sip_emidbg_control()
99 ret = slb_clear_violation((unsigned int)x2); in sip_emidbg_control()
104 ret = emi_clear_violation((unsigned int)x2, (unsigned int)x3); in sip_emidbg_control()
109 ret = slc_parity_select((unsigned int)x2, (unsigned int)x3); in sip_emidbg_control()
112 ret = slc_parity_clear((unsigned int)x2); in sip_emidbg_control()
124 u_register_t x2, in sip_emimpu_control() argument
134 ret = emi_mpu_set_protection((uint32_t)x2, (uint32_t)x3, (unsigned int)x4); in sip_emimpu_control()
137 ret = emi_mpu_set_aid((unsigned int)x2, (unsigned int)x3); in sip_emimpu_control()
[all …]
/rk3399_ARM-atf/plat/st/stm32mp1/services/
H A Dbsec_svc.c18 uint32_t bsec_main(uint32_t x1, uint32_t x2, uint32_t x3, in bsec_main() argument
26 result = bsec_read_otp(ret_otp_value, x2); in bsec_main()
30 result = bsec_program_otp(x3, x2); in bsec_main()
34 result = bsec_write_otp(x3, x2); in bsec_main()
38 result = bsec_read_otp(&tmp_data, x2); in bsec_main()
43 result = bsec_shadow_read_otp(ret_otp_value, x2); in bsec_main()
48 result = bsec_write_otp(tmp_data, x2); in bsec_main()
/rk3399_ARM-atf/plat/arm/board/neoverse_rd/platform/rdv3/
H A Drdv3_per_cpu.S24 adr_l x2, per_cpu_nodes_base
27 add x0, x2, x0, lsl #3
44 mov x2, #PER_CPU_NODE_CORE_COUNT
45 mul x0, x0, x2
50 udiv x0, x1, x2
51 msub x2, x0, x2, x1
62 madd x0, x2, x1, x0
/rk3399_ARM-atf/plat/nxp/soc-ls1028a/aarch64/
H A Dls1028a.S108 mov x2, x0
115 tst x0, x2
207 ldr x2, =NXP_DCFG_ADDR
211 str w1, [x2, #DCFG_BOOTLOCPTRL_OFFSET]
215 str w1, [x2, #DCFG_BOOTLOCPTRH_OFFSET]
256 mov x2, #1
257 lsl x2, x2, x1
262 orr x2, x2, x1
265 orr x2, x2, #ICC_SGI0R_EL1_INTID
268 msr ICC_SGI0R_EL1, x2
[all …]
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t210/
H A Dplat_sip_calls.c43 uint64_t x2, in plat_sip_handler() argument
60 if ((x2 >= TEGRA_PMC_SIZE) || (x2 & 0x3)) { in plat_sip_handler()
64 switch (x2) { in plat_sip_handler()
79 ERROR("%s: error offset=0x%" PRIx64 "\n", __func__, x2); in plat_sip_handler()
88 val = mmio_read_32((uint32_t)(TEGRA_PMC_BASE + x2)); in plat_sip_handler()
91 mmio_write_32((uint32_t)(TEGRA_PMC_BASE + x2), (uint32_t)x3); in plat_sip_handler()
/rk3399_ARM-atf/plat/mediatek/drivers/spm/
H A Dmt_spm_vcorefs_smc.c19 u_register_t x2, in mtk_vcorefs_handler() argument
31 ret = spm_vcorefs_plat_init(x2, x3, &val); in mtk_vcorefs_handler()
46 ret = spm_vcorefs_get_vcore_uv(x2, &val); in mtk_vcorefs_handler()
50 ret = spm_vcorefs_get_dram_freq(x2, &val); in mtk_vcorefs_handler()
62 ret = spm_vcorefs_get_vcore_info(x2, &val); in mtk_vcorefs_handler()
66 ret = spm_vcorefs_qos_mode(x2); in mtk_vcorefs_handler()
70 ret = spm_vcorefs_pause_enable(x2); in mtk_vcorefs_handler()
91 u_register_t x2, in mtk_vcorefs_bl_handler() argument
102 ret = spm_vcorefs_plat_init(x2, x3, &val); in mtk_vcorefs_bl_handler()
/rk3399_ARM-atf/lib/cpus/aarch64/
H A Dwa_cve_2022_23960_bhb.S26 str x2, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
29 mov x2, \_bhb_loop_count
35 subs x2, x2, #1
38 ldr x2, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
/rk3399_ARM-atf/services/std_svc/
H A Dstd_svc_setup.c116 u_register_t x2 = x2_arg; in std_svc_smc_handler() local
124 x2 &= UINT32_MAX; in std_svc_smc_handler()
148 ret = psci_smc_handler(smc_fid, x1, x2, x3, x4, in std_svc_smc_handler()
166 return spm_mm_smc_handler(smc_fid, x1, x2, x3, x4, cookie, in std_svc_smc_handler()
177 return spmd_ffa_smc_handler(smc_fid, x1, x2, x3, x4, cookie, in std_svc_smc_handler()
184 return sdei_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, in std_svc_smc_handler()
191 return trng_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, in std_svc_smc_handler()
198 return errata_abi_smc_handler(smc_fid, x1, x2, x3, x4, cookie, in std_svc_smc_handler()
206 return rmmd_rmm_el3_handler(smc_fid, x1, x2, x3, x4, cookie, in std_svc_smc_handler()
211 return rmmd_rmi_handler(smc_fid, x1, x2, x3, x4, cookie, in std_svc_smc_handler()
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/ufs/
H A Dufs_ctrl.c102 u_register_t x2, in ufs_knl_ctrl() argument
112 ufs_mphy_va09_cg_ctrl(!!x2); in ufs_knl_ctrl()
115 ufs_device_reset_ctrl(!!x2); in ufs_knl_ctrl()
121 ufs_ref_clk_status(x2, x3); in ufs_knl_ctrl()
124 ufs_sram_pwr_ctrl(x2); in ufs_knl_ctrl()
130 ufs_device_pwr_ctrl(x2, x3); in ufs_knl_ctrl()
133 ufs_mphy_ctrl(x2); in ufs_knl_ctrl()
137 ufs_mtcmos_ctrl(!!x2); in ufs_knl_ctrl()
150 u_register_t x2, in ufs_bl_ctrl() argument
160 ufs_device_reset_ctrl(x2); in ufs_bl_ctrl()
/rk3399_ARM-atf/plat/marvell/armada/common/
H A Dmrvl_sip_svc.c75 u_register_t x2, in mrvl_sip_smc_handler() argument
86 __func__, smc_fid, x1, x2, x3); in mrvl_sip_smc_handler()
99 if (x2 >= MAX_LANE_NR) { in mrvl_sip_smc_handler()
101 __func__, smc_fid, x2); in mrvl_sip_smc_handler()
111 ret = mvebu_cp110_comphy_power_on(x1, x2, x3, x5); in mrvl_sip_smc_handler()
115 ret = mvebu_cp110_comphy_power_off(x1, x2, x3); in mrvl_sip_smc_handler()
119 ret = mvebu_cp110_comphy_is_pll_locked(x1, x2); in mrvl_sip_smc_handler()
123 ret = mvebu_cp110_comphy_xfi_rx_training(x1, x2); in mrvl_sip_smc_handler()
127 ret = mvebu_cp110_comphy_digital_reset(x1, x2, x3, x4); in mrvl_sip_smc_handler()
150 ret = mvebu_dfx_thermal_handle(x1, &read, x2, x3); in mrvl_sip_smc_handler()
[all …]
/rk3399_ARM-atf/plat/intel/soc/common/
H A Dsocfpga_sip_svc_v2.c129 u_register_t x2, in sip_smc_handler_v2() argument
147 status = intel_secure_reg_read(x2, &retval); in sip_smc_handler_v2()
148 SMC_RET4(handle, status, x1, retval, x2); in sip_smc_handler_v2()
151 status = intel_secure_reg_write(x2, (uint32_t)x3, &retval); in sip_smc_handler_v2()
152 SMC_RET4(handle, status, x1, retval, x2); in sip_smc_handler_v2()
155 status = intel_secure_reg_update(x2, (uint32_t)x3, in sip_smc_handler_v2()
157 SMC_RET4(handle, status, x1, retval, x2); in sip_smc_handler_v2()
160 status = intel_hps_set_bridges(x2, x3); in sip_smc_handler_v2()
164 status = intel_rsu_update(x2); in sip_smc_handler_v2()
168 status = intel_v2_mbox_send_cmd(x1, (uint32_t *)x2, x3); in sip_smc_handler_v2()
[all …]
/rk3399_ARM-atf/plat/intel/soc/common/aarch64/
H A Dplat_helpers.S47 mov_imm x2, PLAT_CPUID_RELEASE
48 ldr x3, [x2]
103 bic x2, x2, #BS_REG_MAGIC_KEYS_MASK
109 str x2, [x4]
115 lsr x2, x2, #8
118 lsr x2, x2, #8
121 lsr x2, x2, #8
126 bic x2, x2, #BS_REG_MAGIC_KEYS_MASK
127 str x2, [x4]
166 orr x1, x1, x2, lsl #8
[all …]
/rk3399_ARM-atf/plat/hisilicon/hikey/aarch64/
H A Dhikey_helpers.S48 mov_imm x2, PL011_BAUDRATE
89 ldr x2, =0xf7020000
91 str w1, [x2, #4]
93 str w1, [x2, #8]
95 str w1, [x2, #16]
97 str w1, [x2, #32]
99 mrs x2, currentel
100 and x2, x2, #0xc0
102 cmp x2, #0x04
/rk3399_ARM-atf/plat/mediatek/common/
H A Dmtk_sip_svc.c27 u_register_t x2, in mediatek_plat_sip_handler() argument
42 u_register_t x2, in mediatek_sip_handler() argument
52 clean_top_32b_of_param(smc_fid, &x1, &x2, &x3, &x4); in mediatek_sip_handler()
68 (uint32_t)x2); in mediatek_sip_handler()
74 boot_to_kernel(x1, x2, x3, x4); in mediatek_sip_handler()
83 return mediatek_plat_sip_handler(smc_fid, x1, x2, x3, x4, in mediatek_sip_handler()
93 u_register_t x2, in sip_smc_handler() argument
116 return mediatek_sip_handler(smc_fid, x1, x2, x3, x4, in sip_smc_handler()
/rk3399_ARM-atf/plat/hisilicon/hikey960/aarch64/
H A Dhikey960_helpers.S52 mov_imm x2, PL011_BAUDRATE
93 ldr x2, =0xf7020000
95 str w1, [x2, #4]
97 str w1, [x2, #8]
99 str w1, [x2, #16]
101 str w1, [x2, #32]
103 mrs x2, currentel
104 and x2, x2, #0x0c
106 cmp x2, #0x04
/rk3399_ARM-atf/lib/pmf/
H A Dpmf_smc.c19 u_register_t x2, in pmf_smc_handler() argument
30 if (!is_valid_mpidr(x2)) in pmf_smc_handler()
36 x2 = (uint32_t)x2; in pmf_smc_handler()
47 rc = pmf_get_timestamp_smc((unsigned int)x1, x2, in pmf_smc_handler()
65 rc = pmf_get_timestamp_smc((unsigned int)x1, x2, in pmf_smc_handler()
/rk3399_ARM-atf/plat/mediatek/mt8195/
H A Dplat_sip_calls.c20 u_register_t x2, in mediatek_plat_sip_handler() argument
33 ret = emi_mpu_sip_handler(x1, x2, x3); in mediatek_plat_sip_handler()
38 ret = dp_secure_handler(x1, x2, &ret_val); in mediatek_plat_sip_handler()
43 ret = spm_vcorefs_v2_args(x1, x2, x3, &x4); in mediatek_plat_sip_handler()
48 ret = dfd_smc_dispatcher(x1, x2, x3, x4); in mediatek_plat_sip_handler()
53 ret = apusys_kernel_ctrl(x1, x2, x3, x4, &ret_val); in mediatek_plat_sip_handler()

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