| #
2834bc6b |
| 16-May-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fix(tegra210): mark bits [23:17] as zero for Fast SMCs" into integration
|
| #
cb6c8efc |
| 24-Apr-2023 |
Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com> |
fix(tegra210): mark bits [23:17] as zero for Fast SMCs
Per SMCCC documentation, bits [23:17] must be zero for Fast
SMCs. Other values are reserved for future use. Ensure that
these bits are zeroes f
fix(tegra210): mark bits [23:17] as zero for Fast SMCs
Per SMCCC documentation, bits [23:17] must be zero for Fast
SMCs. Other values are reserved for future use. Ensure that
these bits are zeroes for TEGRA_SIP_PMC_COMMANDS.
Commit f8a35797 introduced a check to return error if these
bits are not zero, thus breaking Tegra210 platforms. This
patch fixes the anomaly.
Change-Id: I19edc3b33c999a6fee6b86184233fba146316466
Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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|
| #
ff65ac24 |
| 10-Mar-2023 |
Varun Wadekar <vwadekar@nvidia.com> |
Merge "fix(tegra210): support legacy SMC_ID 0xC2FEFE00" into integration
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| #
40a4e2d8 |
| 31-Jan-2023 |
Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com> |
fix(tegra210): support legacy SMC_ID 0xC2FEFE00
This patch introduces a workaround to support the legacy SMC FID
0xC2FEFE00 to maintain compatibility with older software components.
Change-Id: Icf2
fix(tegra210): support legacy SMC_ID 0xC2FEFE00
This patch introduces a workaround to support the legacy SMC FID
0xC2FEFE00 to maintain compatibility with older software components.
Change-Id: Icf2ef9cfa6b28c09bbab325a642d0b3b20b23535
Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>
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|
| #
28623c10 |
| 08-Nov-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fix: libc: use long for 64-bit types on aarch64" into integration
|
| #
4ce3e99a |
| 25-Aug-2020 |
Scott Branden <scott.branden@broadcom.com> |
fix: libc: use long for 64-bit types on aarch64
Use long instead of long long on aarch64 for 64_t stdint types.
Introduce inttypes.h to properly support printf format specifiers for
fixed width type
fix: libc: use long for 64-bit types on aarch64
Use long instead of long long on aarch64 for 64_t stdint types.
Introduce inttypes.h to properly support printf format specifiers for
fixed width types for such change.
Change-Id: I0bca594687a996fde0a9702d7a383055b99f10a1
Signed-off-by: Scott Branden <scott.branden@broadcom.com>
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|
| #
56887791 |
| 12-Mar-2020 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topic "tegra-downstream-03102020" into integration
* changes:
Tegra210: Remove "unsupported func ID" error msg
Tegra210: support for secure physical timer
spd: tlkd: secure
Merge changes from topic "tegra-downstream-03102020" into integration
* changes:
Tegra210: Remove "unsupported func ID" error msg
Tegra210: support for secure physical timer
spd: tlkd: secure timer interrupt handler
Tegra: smmu: export handlers to read/write SMMU registers
Tegra: smmu: remove context save sequence
Tegra: bpmp: fixup TEGRA_CLK_SE values for Tegra186/Tegra194
Tegra194: memctrl: lock some more MC SID security configs
Tegra194: add SE support to generate SHA256 of TZRAM
Tegra194: store TZDRAM base/size to scratch registers
Tegra194: fix warnings for extra parentheses
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|
| #
b8dbf073 |
| 21-Sep-2018 |
Kalyani Chidambaram <kalyanic@nvidia.com> |
Tegra210: Remove "unsupported func ID" error msg
The platform sip is reporting a "unsupported function ID" if the
smc function id is not pmc command. When actually the smc function id
could be speci
Tegra210: Remove "unsupported func ID" error msg
The platform sip is reporting a "unsupported function ID" if the
smc function id is not pmc command. When actually the smc function id
could be specific to the tegra sip handler.
This patch removes the error reported.
Change-Id: Ia3c8545d345746c5eea6d75b9e6957ca23ae9ca3
Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>
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|
| #
65012c08 |
| 10-Mar-2020 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge changes from topic "tegra-downstream-02182020" into integration
* changes:
Tegra186: store TZDRAM base/size to scratch registers
Tegra186: add SE support to generate SHA256 of TZRAM
Tegr
Merge changes from topic "tegra-downstream-02182020" into integration
* changes:
Tegra186: store TZDRAM base/size to scratch registers
Tegra186: add SE support to generate SHA256 of TZRAM
Tegra186: add support for bpmp_ipc driver
Tegra210: disable ERRATA_A57_829520
Tegra194: memctrl: add support for MIU4 and MIU5
Tegra194: memctrl: remove support to reconfigure MSS
Tegra: fiq_glue: remove bakery locks from interrupt handler
Tegra210: SE: add context save support
Tegra210: update the PMC blacklisted registers
Tegra: disable CPUACTLR access from lower exception levels
cpus: denver: fixup register used to store return address
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|
| #
24902fae |
| 19-Jun-2018 |
kalyani chidambaram <kalyanic@nvidia.com> |
Tegra210: update the PMC blacklisted registers
Update the list to include PMC registers that the NS world cannot
access even with smc calls.
Change-Id: I588179b56ebc0c29200b55e6d61535fd3a7a3b7e
Sig
Tegra210: update the PMC blacklisted registers
Update the list to include PMC registers that the NS world cannot
access even with smc calls.
Change-Id: I588179b56ebc0c29200b55e6d61535fd3a7a3b7e
Signed-off-by: kalyani chidambaram <kalyanic@nvidia.com>
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|
| #
8a08e272 |
| 04-Apr-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1920 from ambroise-arm/av/deprecated
Remove deprecated interfaces
|
| #
6e756f6d |
| 28-Mar-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
Makefile: remove extra include paths in INCLUDES
Now it is needed to use the full path of the common header files.
Commit 09d40e0e0828 ("Sanitise includes across codebase") provides more
informatio
Makefile: remove extra include paths in INCLUDES
Now it is needed to use the full path of the common header files.
Commit 09d40e0e0828 ("Sanitise includes across codebase") provides more
information.
Change-Id: Ifedc79d9f664d208ba565f5736612a3edd94c647
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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|
| #
30490b15 |
| 06-Feb-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1785 from vwadekar/tf2.0-tegra-downstream-rebase-1.25.19
Tf2.0 tegra downstream rebase 1.25.19
|
| #
fdc08e2e |
| 07-Mar-2018 |
kalyani chidambaram <kalyanic@nvidia.com> |
Tegra210: SiP handlers to allow PMC access
This patch adds SiP handler for Tegra210 platforms to service
read/write requests for PMC block. None of the secure registers
are accessible to the NS worl
Tegra210: SiP handlers to allow PMC access
This patch adds SiP handler for Tegra210 platforms to service
read/write requests for PMC block. None of the secure registers
are accessible to the NS world though.
Change-Id: I7dc1f10c6a6ee6efc642ddcfb1170fb36d3accff
Signed-off-by: kalyani chidambaram <kalyanic@nvidia.com>
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|
| #
87bf3c62 |
| 23-Feb-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #845 from vwadekar/tegra-changes-from-downstream-v1
Tegra changes from downstream v1
|
| #
f9b895ad |
| 03-Sep-2015 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: SoC specific SiP handlers
This patch converts the common SiP handler to SoC specific SiP
handler. T210 and T132 have different SiP SMCs and so it makes
sense to move the SiP handler to soc/t1
Tegra: SoC specific SiP handlers
This patch converts the common SiP handler to SoC specific SiP
handler. T210 and T132 have different SiP SMCs and so it makes
sense to move the SiP handler to soc/t132 and soc/t210 folders.
Change-Id: Idfe48384d63641137d74a095432df4724986b241
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
show more ...
|