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Searched refs:vectors (Results 1 – 19 of 19) sorted by relevance

/rk3399_ARM-atf/plat/marvell/armada/a8k/a80x0_nbx/board/
H A Dramoopsies.c57 static uint32_t vectors[512] __aligned(2048) = { variable
87 write_vbar_el3((u_register_t)vectors); in clear_serror()
/rk3399_ARM-atf/include/lib/el3_runtime/
H A Dsimd_ctx.h56 uint8_t vectors[32][SIMD_VECTOR_LEN_BYTES]; member
72 CASSERT(CTX_SIMD_VECTORS == __builtin_offsetof(simd_regs_t, vectors),
/rk3399_ARM-atf/bl32/tsp/
H A Dtsp.ld.S35 *(.vectors)
68 *(.vectors)
/rk3399_ARM-atf/bl2u/
H A Dbl2u.ld.S37 *(.vectors)
77 *(.vectors)
/rk3399_ARM-atf/bl2/
H A Dbl2.ld.S36 *(.vectors)
78 *(.vectors)
H A Dbl2_el3.ld.S76 *(.vectors)
118 *(.vectors)
/rk3399_ARM-atf/bl32/sp_min/
H A Dsp_min.ld.S40 *(.vectors)
89 *(.vectors)
/rk3399_ARM-atf/bl1/
H A Dbl1.ld.S46 *(.vectors)
97 *(.vectors)
/rk3399_ARM-atf/bl31/
H A Dbl31.ld.S54 *(.vectors)
99 *(.vectors)
/rk3399_ARM-atf/plat/amd/versal2/
H A Dplat.ld.S.tpl28 *(.text*) *(.vectors)
/rk3399_ARM-atf/include/arch/aarch64/
H A Dasm_macros.S107 .macro vector_base label, section_name=.vectors
120 .macro vector_entry label, section_name=.vectors
/rk3399_ARM-atf/plat/nvidia/tegra/scat/
H A Dbl31.scat30 *(.vectors)
102 * Exception vectors of the SPM shim layer. They must be aligned to a 2K
/rk3399_ARM-atf/docs/components/spd/
H A Doptee-dispatcher.rst21 kernel finishes loading and before any attack vectors can be opened up by
/rk3399_ARM-atf/include/arch/aarch32/
H A Dasm_macros.S67 .section .vectors, "ax"
/rk3399_ARM-atf/docs/about/
H A Dfeatures.rst14 - Initialization of the secure world, for example exception vectors, control
/rk3399_ARM-atf/docs/design/
H A Dreset-design.rst117 SRAM and all CPU reset vectors be changed from the default ``0x0`` to this run
H A Dinterrupt-framework-design.rst531 triggered at one of the Secure-EL1 FIQ exception vectors. The Secure-EL1
558 triggered at one of the Secure-EL1 IRQ exception vectors . The Secure-EL1
620 The EL3 runtime firmware populates the IRQ and FIQ exception vectors referenced
923 non-secure and Secure-EL1 interrupts at the IRQ and FIQ vectors in its exception
H A Dfirmware-design.rst177 - Exception vectors
179 BL1 sets up simple exception vectors for both synchronous and asynchronous
504 It then replaces the exception vectors populated by BL1 with its own. BL31
505 exception vectors implement more elaborate support for handling SMCs since this
1159 For ARM architecture, exception vectors are stored in a table, called the exception
2424 | Exception vectors |
2434 The 2KB alignment for the exception vectors is an architectural
2459 code and exception vectors are now contiguous, like so:
2473 | Exception vectors |
/rk3399_ARM-atf/docs/
H A Dchange-log.md10807 - allwinner: Adjust SRAM A2 base to include the ARISC vectors, clean up MMU
12942 - Removed the separate `early_exception` vectors from BL3-1 (2KB code size