| #
7303319b |
| 08-Nov-2025 |
Chris Kay <chris.kay@arm.com> |
Merge changes from topic "NUMA_AWARE_PER_CPU" into integration
* changes: docs(maintainers): add per-cpu framework into maintainers.rst feat(per-cpu): add documentation for per-cpu framework f
Merge changes from topic "NUMA_AWARE_PER_CPU" into integration
* changes: docs(maintainers): add per-cpu framework into maintainers.rst feat(per-cpu): add documentation for per-cpu framework feat(rdv3): enable numa aware per-cpu for RD-V3-Cfg2 feat(per-cpu): migrate amu_ctx to per-cpu framework feat(per-cpu): migrate spm_core_context to per-cpu framework feat(per-cpu): migrate psci_ns_context to per-cpu framework feat(per-cpu): migrate psci_cpu_pd_nodes to per-cpu framework feat(per-cpu): migrate rmm_context to per-cpu framework feat(per-cpu): integrate per-cpu framework into BL31/BL32 feat(per-cpu): introduce framework accessors/definers feat(per-cpu): introduce linker changes for NUMA aware per-cpu framework docs(changelog): add scope for per-cpu framework
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| #
7256cf0a |
| 29-Jan-2025 |
Rohit Mathew <rohit.mathew@arm.com> |
feat(per-cpu): introduce linker changes for NUMA aware per-cpu framework
This commit introduces linker changes for NUMA aware per-cpu objects in the BL31 and BL32 images. The per-cpu framework is de
feat(per-cpu): introduce linker changes for NUMA aware per-cpu framework
This commit introduces linker changes for NUMA aware per-cpu objects in the BL31 and BL32 images. The per-cpu framework is designed to minimise cache thrashing, and the linker layout ensures each CPU’s per-cpu data is placed on a separate cache line. This isolation is expected to improve performance when the per-cpu framework is enabled.
Signed-off-by: Sammit Joshi <sammit.joshi@arm.com> Signed-off-by: Rohit Mathew <rohit.mathew@arm.com> Change-Id: Ie4d8b4e444971adbd9dba0446d1ab8cafaca1556
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| #
8ddb02d5 |
| 30-Nov-2023 |
André Przywara <andre.przywara@arm.com> |
Merge changes from topic "fix-lto-build" into integration
* changes: fix(build): don't generate build-id fix(build): add forgotten BL_LDFLAGS to lto command line feat(build): check that .text
Merge changes from topic "fix-lto-build" into integration
* changes: fix(build): don't generate build-id fix(build): add forgotten BL_LDFLAGS to lto command line feat(build): check that .text section starts at page boundary
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| #
3d6edc32 |
| 05-Sep-2023 |
Andrey Skvortsov <andrej.skvortzov@gmail.com> |
feat(build): check that .text section starts at page boundary
Linker may decide to put new unspecified sections before .text section. That will cause non-working image, because entry point isn't at
feat(build): check that .text section starts at page boundary
Linker may decide to put new unspecified sections before .text section. That will cause non-working image, because entry point isn't at __BLXX_START__. Device just not booted with such image.
This happened for example with .note.gnu.build-id section generated for LTO build in some cases. Now linker will report this situation as an error.
``` /usr/lib/gcc-cross/aarch64-linux-gnu/13/../../../../aarch64-linux-gnu/bin/ld: .text is not aligned on a page boundary. collect2: error: ld returned 1 exit status ```
Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com> Change-Id: I5ae46ddd1e6e431e1df1715d1d301f6dd7181cc7
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| #
7ae96dce |
| 12-Jun-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "chore(bl): add UNALIGNED symbols for TEXT/RODATA" into integration
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| #
f7d445fc |
| 27-Apr-2023 |
Michal Simek <michal.simek@amd.com> |
chore(bl): add UNALIGNED symbols for TEXT/RODATA
Add symbols to mark end of TEXT/RODATA before page alignment. Similar change was done by commit 8d69a03f6a7d ("Various improvements/cleanups on the l
chore(bl): add UNALIGNED symbols for TEXT/RODATA
Add symbols to mark end of TEXT/RODATA before page alignment. Similar change was done by commit 8d69a03f6a7d ("Various improvements/cleanups on the linker scripts") for RO_END/COHERENT_RAM. These symbols help to know how much free space is in the final binary because of page alignment.
Also show all *UNALIGNED__ symbols via poetry. For example: poetry run memory -p zynqmp -b debug
Change-Id: I322beba37dad76be9f4e88ca7e5b3eff2df7d96e Signed-off-by: Michal Simek <michal.simek@amd.com>
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| #
9b5c0fcd |
| 01-Jun-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topic "hm/memmap-feat" into integration
* changes: build(bl32): add symbols for memory layout build(bl31): add symbols for memory layout build(bl2): add symbols for memory l
Merge changes from topic "hm/memmap-feat" into integration
* changes: build(bl32): add symbols for memory layout build(bl31): add symbols for memory layout build(bl2): add symbols for memory layout build(bl1): add symbols for memory layout refactor: improve readability of symbol table
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| #
fcb72e16 |
| 19-Apr-2023 |
Harrison Mutai <harrison.mutai@arm.com> |
build(bl32): add symbols for memory layout
Add symbols for mapping the physical memory layout of BL32. There are symbols that partially satisfy this requirement, however, the naming of these is inco
build(bl32): add symbols for memory layout
Add symbols for mapping the physical memory layout of BL32. There are symbols that partially satisfy this requirement, however, the naming of these is inconsistent.
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com> Change-Id: I106187f93b227d604bda650892f9e919047b3fc7
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| #
338dbe2f |
| 22-Feb-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes I51c13c52,I3358c51e into integration
* changes: build: always prefix section names with `.` build: communicate correct page size to linker
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| #
da04341e |
| 14-Feb-2023 |
Chris Kay <chris.kay@arm.com> |
build: always prefix section names with `.`
Some of our specialized sections are not prefixed with the conventional period. The compiler uses input section names to derive certain other section name
build: always prefix section names with `.`
Some of our specialized sections are not prefixed with the conventional period. The compiler uses input section names to derive certain other section names (e.g. `.rela.text`, `.relacpu_ops`), and these can be difficult to select in linker scripts when there is a lack of a delimiter.
This change introduces the period prefix to all specialized section names.
BREAKING-CHANGE: All input and output linker section names have been prefixed with the period character, e.g. `cpu_ops` -> `.cpu_ops`.
Change-Id: I51c13c5266d5975fbd944ef4961328e72f82fc1c Signed-off-by: Chris Kay <chris.kay@arm.com>
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| #
3cc02562 |
| 13-Feb-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes from topic "mixed-rwx" into integration
* changes: build: permit multiple linker scripts build: clarify linker script generation style: normalize linker script code style fix(p
Merge changes from topic "mixed-rwx" into integration
* changes: build: permit multiple linker scripts build: clarify linker script generation style: normalize linker script code style fix(pie): pass `-fpie` to the preprocessor as well
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| #
f90fe02f |
| 29-Sep-2022 |
Chris Kay <chris.kay@arm.com> |
style: normalize linker script code style
There are a variety of code styles used by the various linker scripts around the code-base. This change brings them in line with one another and attempts to
style: normalize linker script code style
There are a variety of code styles used by the various linker scripts around the code-base. This change brings them in line with one another and attempts to make the scripts more friendly for skim-readers.
Change-Id: Ibee2afad0d543129c9ba5a8a22e3ec17d77e36ea Signed-off-by: Chris Kay <chris.kay@arm.com>
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| #
08e7cc53 |
| 29-Apr-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes I15e7cc43,Id7411bd5,I92bafe70,I8f1c0658 into integration
* changes: stm32mp1: enable PIE for BL32 stm32mp1: set BL sizes regardless of flags Add PIE support for AARCH32 Avoid t
Merge changes I15e7cc43,Id7411bd5,I92bafe70,I8f1c0658 into integration
* changes: stm32mp1: enable PIE for BL32 stm32mp1: set BL sizes regardless of flags Add PIE support for AARCH32 Avoid the use of linker *_SIZE__ macros
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| #
4324a14b |
| 05-Oct-2020 |
Yann Gautier <yann.gautier@st.com> |
Add PIE support for AARCH32
Only BL32 (SP_min) is supported at the moment, BL1 and BL2_AT_EL3 are just stubbed with _pie_fixup_size=0. The changes are an adaptation for AARCH32 on what has been done
Add PIE support for AARCH32
Only BL32 (SP_min) is supported at the moment, BL1 and BL2_AT_EL3 are just stubbed with _pie_fixup_size=0. The changes are an adaptation for AARCH32 on what has been done for PIE support on AARCH64. The RELA_SECTION is redefined for AARCH32, as the created section is .rel.dyn and the symbols are .rel*.
Change-Id: I92bafe70e6b77735f6f890f32f2b637b98cf01b9 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| #
3bddca4b |
| 15-Oct-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes I0005959b,I2ea59edb into integration
* changes: bl32: add an assert on BL32_SIZE in sp_min.ld.S bl32: use SORT_BY_ALIGNMENT macro in sp_min.ld.S
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| #
fdd97d7c |
| 05-Oct-2020 |
Yann Gautier <yann.gautier@st.com> |
bl32: add an assert on BL32_SIZE in sp_min.ld.S
This assert is present in all other linker scripts. This checks the size of BL32 doesn't exceed its defined limit.
Change-Id: I0005959b5591d3eebd8700
bl32: add an assert on BL32_SIZE in sp_min.ld.S
This assert is present in all other linker scripts. This checks the size of BL32 doesn't exceed its defined limit.
Change-Id: I0005959b5591d3eebd870045adafe437108bc9e1 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| #
b1f596b6 |
| 05-Oct-2020 |
Yann Gautier <yann.gautier@st.com> |
bl32: use SORT_BY_ALIGNMENT macro in sp_min.ld.S
The macro SORT_BY_ALIGNMENT is used for .text* and .rodata*. This allows reducing the space lost to object alignment. This is an alignment with the f
bl32: use SORT_BY_ALIGNMENT macro in sp_min.ld.S
The macro SORT_BY_ALIGNMENT is used for .text* and .rodata*. This allows reducing the space lost to object alignment. This is an alignment with the following patch: ebd6efae67c6a086bc97d807a638bde324d936dc
Some comments are also aligned with other linker scripts.
Change-Id: I2ea59edb445af0ed8c08fd883ffbf56852570d0c Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| #
455a6f3b |
| 27-Apr-2020 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topic "linker-script" into integration
* changes: linker_script: move .data section to bl_common.ld.h linker_script: move stacks section to bl_common.ld.h bl1: remove '.' fr
Merge changes from topic "linker-script" into integration
* changes: linker_script: move .data section to bl_common.ld.h linker_script: move stacks section to bl_common.ld.h bl1: remove '.' from stacks section in linker script
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| #
caa3e7e0 |
| 22-Apr-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
linker_script: move .data section to bl_common.ld.h
Move the data section to the common header.
I slightly tweaked some scripts as follows:
[1] bl1.ld.S has ALIGN(16). I added DATA_ALIGN macro, wh
linker_script: move .data section to bl_common.ld.h
Move the data section to the common header.
I slightly tweaked some scripts as follows:
[1] bl1.ld.S has ALIGN(16). I added DATA_ALIGN macro, which is 1 by default, but overridden by bl1.ld.S. Currently, ALIGN(16) of the .data section is redundant because commit 412865907699 ("Fix boot failures on some builds linked with ld.lld.") padded out the previous section to work around the issue of LLD version <= 10.0. This will be fixed in the future release of LLVM, so I am keeping the proper way to align LMA.
[2] bl1.ld.S and bl2_el3.ld.S define __DATA_RAM_{START,END}__ instead of __DATA_{START,END}__. I put them out of the .data section.
[3] SORT_BY_ALIGNMENT() is missing tsp.ld.S, sp_min.ld.S, and mediatek/mt6795/bl31.ld.S. This commit adds SORT_BY_ALIGNMENT() for all images, so the symbol order in those three will change, but I do not think it is a big deal.
Change-Id: I215bb23c319f045cd88e6f4e8ee2518c67f03692 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| #
a926a9f6 |
| 07-Apr-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
linker_script: move stacks section to bl_common.ld.h
The stacks section is the same for all BL linker scripts.
Move it to the common header file.
Change-Id: Ibd253488667ab4f69702d56ff9e9929376704f
linker_script: move stacks section to bl_common.ld.h
The stacks section is the same for all BL linker scripts.
Move it to the common header file.
Change-Id: Ibd253488667ab4f69702d56ff9e9929376704f6c Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| #
ea7fc9d1 |
| 02-Apr-2020 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topic "xlat" into integration
* changes: xlat_tables_v2: fix assembler warning of PLAT_RO_XLAT_TABLES linker_script: move bss section to bl_common.ld.h linker_script: replac
Merge changes from topic "xlat" into integration
* changes: xlat_tables_v2: fix assembler warning of PLAT_RO_XLAT_TABLES linker_script: move bss section to bl_common.ld.h linker_script: replace common read-only data with RODATA_COMMON linker_script: move more common code to bl_common.ld.h
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| #
a7739bc7 |
| 26-Mar-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
linker_script: move bss section to bl_common.ld.h
Move the bss section to the common header. This adds BAKERY_LOCK_NORMAL and PMF_TIMESTAMP, which previously existed only in BL31. This is not a big
linker_script: move bss section to bl_common.ld.h
Move the bss section to the common header. This adds BAKERY_LOCK_NORMAL and PMF_TIMESTAMP, which previously existed only in BL31. This is not a big deal because unused data should not be compiled in the first place. I believe this should be controlled by BL*_SOURCES in Makefiles, not by linker scripts.
I investigated BL1, BL2, BL2U, BL31 for plat=fvp, and BL2-AT-EL3, BL31, BL31 for plat=uniphier. I did not see any more unexpected code addition.
The bss section has bigger alignment. I added BSS_ALIGN for this.
Currently, SORT_BY_ALIGNMENT() is missing in sp_min.ld.S, and with this change, the BSS symbols in SP_MIN will be sorted by the alignment. This is not a big deal (or, even better in terms of the image size).
Change-Id: I680ee61f84067a559bac0757f9d03e73119beb33 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| #
0a0a7a9a |
| 26-Mar-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
linker_script: replace common read-only data with RODATA_COMMON
The common section data are repeated in many linker scripts (often twice in each script to support SEPARATE_CODE_AND_RODATA). When you
linker_script: replace common read-only data with RODATA_COMMON
The common section data are repeated in many linker scripts (often twice in each script to support SEPARATE_CODE_AND_RODATA). When you add a new read-only data section, you end up with touching lots of places.
After this commit, you will only need to touch bl_common.ld.h when you add a new section to RODATA_COMMON.
Replace a series of RO section with RODATA_COMMON, which contains 6 sections, some of which did not exist before.
This is not a big deal because unneeded data should not be compiled in the first place. I believe this should be controlled by BL*_SOURCES in Makefiles, not by linker scripts.
When I was working on this commit, the BL1 image size increased due to the fconf_populator. Commit c452ba159c14 ("fconf: exclude fconf_dyn_cfg_getter.c from BL1_SOURCES") fixed this issue.
I investigated BL1, BL2, BL2U, BL31 for plat=fvp, and BL2-AT-EL3, BL31, BL31 for plat=uniphier. I did not see any more unexpected code addition.
Change-Id: I5d14d60dbe3c821765bce3ae538968ef266f1460 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| #
9fb288a0 |
| 26-Mar-2020 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
linker_script: move more common code to bl_common.ld.h
These are mostly used to collect data from special structure, and repeated in many linker scripts.
To differentiate the alignment size between
linker_script: move more common code to bl_common.ld.h
These are mostly used to collect data from special structure, and repeated in many linker scripts.
To differentiate the alignment size between aarch32/aarch64, I added a new macro STRUCT_ALIGN.
While I moved the PMF_SVC_DESCS, I dropped #if ENABLE_PMF conditional. As you can see in include/lib/pmf/pmf_helpers.h, PMF_REGISTER_SERVICE* are no-op when ENABLE_PMF=0. So, pmf_svc_descs and pmf_timestamp_array data are not populated.
Change-Id: I3f4ab7fa18f76339f1789103407ba76bda7e56d0 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| #
0603a064 |
| 31-Mar-2020 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Merge "bl32: sp_min: reduce the alignment for fconf_populator" into integration
|