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Searched refs:table_pll (Results 1 – 25 of 26) sorted by relevance

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/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/
H A Dmt_spm_cond.c46 res->table_pll = (src->table_pll & dest->table_pll); in mt_spm_cond_check()
48 if (res->table_pll) in mt_spm_cond_check()
49 b_res |= (res->table_pll << SPM_COND_BLOCKED_PLL_IDX) | in mt_spm_cond_check()
51 } else if (src->table_pll & dest->table_pll) in mt_spm_cond_check()
64 res->table_pll = src->table_pll; in mt_spm_dump_all_pll()
65 if (res->table_pll) in mt_spm_dump_all_pll()
66 b_res |= (res->table_pll << SPM_COND_BLOCKED_PLL_IDX) | in mt_spm_dump_all_pll()
68 } else if (src->table_pll & dest->table_pll) in mt_spm_dump_all_pll()
119 spm_cond->table_pll = 0; in mt_spm_cond_update()
123 spm_cond->table_pll |= pll_table[i].pll_bit_set; in mt_spm_cond_update()
H A Dmt_spm_cond.h73 uint64_t table_pll; member
/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spm/
H A Dmt_spm_cond.c129 res->table_pll = (src->table_pll & dest->table_pll); in mt_spm_cond_check()
131 if (res->table_pll != 0U) { in mt_spm_cond_check()
132 blocked |= (res->table_pll << SPM_COND_BLOCKED_PLL_IDX) | in mt_spm_cond_check()
135 } else if ((src->table_pll & dest->table_pll) != 0U) { in mt_spm_cond_check()
177 spm_cond_t.table_pll = 0U; in mt_spm_cond_update()
179 spm_cond_t.table_pll |= PLL_BIT_MFGPLL; in mt_spm_cond_update()
183 spm_cond_t.table_pll |= PLL_BIT_MMPLL; in mt_spm_cond_update()
187 spm_cond_t.table_pll |= PLL_BIT_UNIVPLL; in mt_spm_cond_update()
191 spm_cond_t.table_pll |= PLL_BIT_MSDCPLL; in mt_spm_cond_update()
195 spm_cond_t.table_pll |= PLL_BIT_TVDPLL; in mt_spm_cond_update()
H A Dmt_spm_cond.h48 unsigned int table_pll; member
/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spm/
H A Dmt_spm_cond.c135 res->table_pll = (src->table_pll & dest->table_pll); in mt_spm_cond_check()
137 if (res->table_pll != 0U) { in mt_spm_cond_check()
139 (res->table_pll << SPM_COND_BLOCKED_PLL_IDX) | in mt_spm_cond_check()
142 } else if ((src->table_pll & dest->table_pll) != 0U) { in mt_spm_cond_check()
184 spm_cond_t.table_pll = 0U; in mt_spm_cond_update()
186 spm_cond_t.table_pll |= PLL_BIT_MFGPLL; in mt_spm_cond_update()
190 spm_cond_t.table_pll |= PLL_BIT_MMPLL; in mt_spm_cond_update()
194 spm_cond_t.table_pll |= PLL_BIT_UNIVPLL; in mt_spm_cond_update()
198 spm_cond_t.table_pll |= PLL_BIT_MSDCPLL; in mt_spm_cond_update()
202 spm_cond_t.table_pll |= PLL_BIT_TVDPLL; in mt_spm_cond_update()
H A Dmt_spm_cond.h46 unsigned int table_pll; member
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spm/
H A Dmt_spm_cond.c152 res->table_pll = (src->table_pll & dest->table_pll); in mt_spm_cond_check()
154 if (res->table_pll != 0U) { in mt_spm_cond_check()
156 (res->table_pll << SPM_COND_BLOCKED_PLL_IDX) | in mt_spm_cond_check()
159 } else if ((src->table_pll & dest->table_pll) != 0U) { in mt_spm_cond_check()
200 spm_cond_t.table_pll = 0U; in mt_spm_cond_update()
202 spm_cond_t.table_pll |= PLL_BIT_MFGPLL; in mt_spm_cond_update()
206 spm_cond_t.table_pll |= PLL_BIT_MMPLL; in mt_spm_cond_update()
210 spm_cond_t.table_pll |= PLL_BIT_UNIVPLL; in mt_spm_cond_update()
214 spm_cond_t.table_pll |= PLL_BIT_MSDCPLL; in mt_spm_cond_update()
218 spm_cond_t.table_pll |= PLL_BIT_TVDPLL; in mt_spm_cond_update()
H A Dmt_spm_cond.h63 unsigned int table_pll; member
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8188/
H A Dmt_spm_cond.c161 res->table_pll = (src->table_pll & dest->table_pll); in mt_spm_cond_check()
163 if ((res->table_pll) != 0U) { in mt_spm_cond_check()
164 b_res |= (res->table_pll << SPM_COND_BLOCKED_PLL_IDX) | in mt_spm_cond_check()
167 } else if ((src->table_pll & dest->table_pll) != 0U) { in mt_spm_cond_check()
190 } else if ((src->table_pll & dest->table_pll) != 0U) { in mt_spm_dump_all_pll()
244 spm_cond_t.table_pll = 0U; in mt_spm_cond_update()
247 spm_cond_t.table_pll |= plls[i].pll_b; in mt_spm_cond_update()
H A Dmt_spm_cond.h80 unsigned int table_pll; member
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/constraints/
H A Dmt_spm_rc_api.c41 tlb->table_pll |= (cond << pll_idx); in spm_rc_condition_modifier()
43 tlb->table_pll &= ~(cond << pll_idx); in spm_rc_condition_modifier()
H A Dmt_spm_rc_vcore.c53 .table_pll = (PLL_BIT_MFG | PLL_BIT_MFGSC),
57 .table_pll = 0,
H A Dmt_spm_rc_bus26m.c59 .table_pll = (PLL_BIT_MFG | PLL_BIT_MFGSC),
63 .table_pll = 0,
/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spm/constraints/
H A Dmt_spm_rc_dram.c58 .table_pll = 0U,
63 .table_pll = 0U,
H A Dmt_spm_rc_syspll.c63 .table_pll = 0U,
68 .table_pll = 0U,
H A Dmt_spm_rc_bus26m.c72 .table_pll = (PLL_BIT_UNIVPLL | PLL_BIT_MFGPLL |
79 .table_pll = 0U,
/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spm/constraints/
H A Dmt_spm_rc_syspll.c57 .table_pll = 0U,
62 .table_pll = 0U,
H A Dmt_spm_rc_dram.c58 .table_pll = 0U,
63 .table_pll = 0U,
H A Dmt_spm_rc_bus26m.c68 .table_pll = (PLL_BIT_UNIVPLL | PLL_BIT_MFGPLL |
75 .table_pll = 0U,
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spm/constraints/
H A Dmt_spm_rc_dram.c67 .table_pll = 0U,
72 .table_pll = 0U,
H A Dmt_spm_rc_syspll.c65 .table_pll = 0U,
70 .table_pll = 0U,
H A Dmt_spm_rc_bus26m.c76 .table_pll = (PLL_BIT_UNIVPLL |
85 .table_pll = 0U,
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8188/constraints/
H A Dmt_spm_rc_api.c45 SPM_RC_BITS_SET(tlb->table_pll, (cond << pll_idx)); in spm_rc_condition_modifier()
47 SPM_RC_BITS_CLR(tlb->table_pll, (cond << pll_idx)); in spm_rc_condition_modifier()
H A Dmt_spm_rc_dram.c60 .table_pll = 0U,
65 .table_pll = 0U,
H A Dmt_spm_rc_syspll.c72 .table_pll = 0U,
77 .table_pll = 0U,

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